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Structure type to access the System Control Block (SCB). More...
#include <arch/cpu/arm/cortex-m/CMSIS/core_cm0.h>
Data Fields | |
__IM uint32_t | CPUID |
__IOM uint32_t | ICSR |
__IOM uint32_t | AIRCR |
__IOM uint32_t | SCR |
__IOM uint32_t | CCR |
__IOM uint32_t | SHP [2U] |
__IOM uint32_t | SHCSR |
__IOM uint32_t | VTOR |
__IOM uint8_t | SHP [12U] |
__IOM uint32_t | CFSR |
__IOM uint32_t | HFSR |
__IOM uint32_t | DFSR |
__IOM uint32_t | MMFAR |
__IOM uint32_t | BFAR |
__IOM uint32_t | AFSR |
__IM uint32_t | PFR [2U] |
__IM uint32_t | DFR |
__IM uint32_t | ADR |
__IM uint32_t | MMFR [4U] |
__IM uint32_t | ISAR [5U] |
__IOM uint32_t | CPACR |
__IOM uint8_t | SHPR [12U] |
__IM uint32_t | ID_PFR [2U] |
__IM uint32_t | ID_DFR |
__IM uint32_t | ID_AFR |
__IM uint32_t | ID_MFR [4U] |
__IM uint32_t | ID_ISAR [5U] |
__IM uint32_t | CLIDR |
__IM uint32_t | CTR |
__IM uint32_t | CCSIDR |
__IOM uint32_t | CSSELR |
__OM uint32_t | STIR |
__IM uint32_t | MVFR0 |
__IM uint32_t | MVFR1 |
__IM uint32_t | MVFR2 |
__OM uint32_t | ICIALLU |
__OM uint32_t | ICIMVAU |
__OM uint32_t | DCIMVAC |
__OM uint32_t | DCISW |
__OM uint32_t | DCCMVAU |
__OM uint32_t | DCCMVAC |
__OM uint32_t | DCCSW |
__OM uint32_t | DCCIMVAC |
__OM uint32_t | DCCISW |
__IOM uint32_t | ITCMCR |
__IOM uint32_t | DTCMCR |
__IOM uint32_t | AHBPCR |
__IOM uint32_t | CACR |
__IOM uint32_t | AHBSCR |
__IOM uint32_t | ABFSR |
__IOM uint32_t | SFCR |
Structure type to access the System Control Block (SCB).
Definition at line 389 of file core_cm0.h.
__IOM uint32_t SCB_Type::ABFSR |
Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register
Definition at line 551 of file core_cm7.h.
__IM uint32_t SCB_Type::ADR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
Definition at line 435 of file core_cm3.h.
__IOM uint32_t SCB_Type::AFSR |
Offset: 0x03C (R/W) Auxiliary Fault Status Register
Definition at line 432 of file core_cm3.h.
__IOM uint32_t SCB_Type::AHBPCR |
Offset: 0x298 (R/W) AHBP Control Register
Definition at line 547 of file core_cm7.h.
__IOM uint32_t SCB_Type::AHBSCR |
Offset: 0x2A0 (R/W) AHB Slave Control Register
Definition at line 549 of file core_cm7.h.
__IOM uint32_t SCB_Type::AIRCR |
Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
Definition at line 394 of file core_cm0.h.
__IOM uint32_t SCB_Type::BFAR |
Offset: 0x038 (R/W) BusFault Address Register
Definition at line 431 of file core_cm3.h.
__IOM uint32_t SCB_Type::CACR |
Offset: 0x29C (R/W) L1 Cache Control Register
Definition at line 548 of file core_cm7.h.
__IOM uint32_t SCB_Type::CCR |
Offset: 0x014 (R/W) Configuration Control Register
Definition at line 396 of file core_cm0.h.
__IM uint32_t SCB_Type::CCSIDR |
Offset: 0x080 (R/ ) Cache Size ID Register
Definition at line 524 of file core_cm7.h.
__IOM uint32_t SCB_Type::CFSR |
Offset: 0x028 (R/W) Configurable Fault Status Register
Definition at line 427 of file core_cm3.h.
__IM uint32_t SCB_Type::CLIDR |
Offset: 0x078 (R/ ) Cache Level ID register
Definition at line 522 of file core_cm7.h.
__IOM uint32_t SCB_Type::CPACR |
Offset: 0x088 (R/W) Coprocessor Access Control Register
Definition at line 439 of file core_cm3.h.
__IM uint32_t SCB_Type::CPUID |
Offset: 0x000 (R/ ) CPUID Base Register
Definition at line 391 of file core_cm0.h.
__IOM uint32_t SCB_Type::CSSELR |
Offset: 0x084 (R/W) Cache Size Selection Register
Definition at line 525 of file core_cm7.h.
__IM uint32_t SCB_Type::CTR |
Offset: 0x07C (R/ ) Cache Type register
Definition at line 523 of file core_cm7.h.
__OM uint32_t SCB_Type::DCCIMVAC |
Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC
Definition at line 542 of file core_cm7.h.
__OM uint32_t SCB_Type::DCCISW |
Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way
Definition at line 543 of file core_cm7.h.
__OM uint32_t SCB_Type::DCCMVAC |
Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC
Definition at line 540 of file core_cm7.h.
__OM uint32_t SCB_Type::DCCMVAU |
Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU
Definition at line 539 of file core_cm7.h.
__OM uint32_t SCB_Type::DCCSW |
Offset: 0x26C ( /W) D-Cache Clean by Set-way
Definition at line 541 of file core_cm7.h.
__OM uint32_t SCB_Type::DCIMVAC |
Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC
Definition at line 537 of file core_cm7.h.
__OM uint32_t SCB_Type::DCISW |
Offset: 0x260 ( /W) D-Cache Invalidate by Set-way
Definition at line 538 of file core_cm7.h.
__IM uint32_t SCB_Type::DFR |
Offset: 0x048 (R/ ) Debug Feature Register
Definition at line 434 of file core_cm3.h.
__IOM uint32_t SCB_Type::DFSR |
Offset: 0x030 (R/W) Debug Fault Status Register
Definition at line 429 of file core_cm3.h.
__IOM uint32_t SCB_Type::DTCMCR |
Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers
Definition at line 546 of file core_cm7.h.
__IOM uint32_t SCB_Type::HFSR |
Offset: 0x02C (R/W) HardFault Status Register
Definition at line 428 of file core_cm3.h.
__OM uint32_t SCB_Type::ICIALLU |
Offset: 0x250 ( /W) I-Cache Invalidate All to PoU
Definition at line 534 of file core_cm7.h.
__OM uint32_t SCB_Type::ICIMVAU |
Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU
Definition at line 536 of file core_cm7.h.
__IOM uint32_t SCB_Type::ICSR |
Offset: 0x004 (R/W) Interrupt Control and State Register
Definition at line 392 of file core_cm0.h.
__IM uint32_t SCB_Type::ID_AFR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
Definition at line 518 of file core_cm7.h.
__IM uint32_t SCB_Type::ID_DFR |
Offset: 0x048 (R/ ) Debug Feature Register
Definition at line 517 of file core_cm7.h.
__IM uint32_t SCB_Type::ID_ISAR[5U] |
Offset: 0x060 (R/ ) Instruction Set Attributes Register
Definition at line 520 of file core_cm7.h.
__IM uint32_t SCB_Type::ID_MFR[4U] |
Offset: 0x050 (R/ ) Memory Model Feature Register
Definition at line 519 of file core_cm7.h.
__IM uint32_t SCB_Type::ID_PFR[2U] |
Offset: 0x040 (R/ ) Processor Feature Register
Definition at line 516 of file core_cm7.h.
__IM uint32_t SCB_Type::ISAR |
Offset: 0x060 (R/ ) Instruction Set Attributes Register
Definition at line 437 of file core_cm3.h.
__IOM uint32_t SCB_Type::ITCMCR |
Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register
Definition at line 545 of file core_cm7.h.
__IOM uint32_t SCB_Type::MMFAR |
Offset: 0x034 (R/W) MemManage Fault Address Register
Definition at line 430 of file core_cm3.h.
__IM uint32_t SCB_Type::MMFR |
Offset: 0x050 (R/ ) Memory Model Feature Register
Definition at line 436 of file core_cm3.h.
__IM uint32_t SCB_Type::MVFR0 |
Offset: 0x240 (R/ ) Media and VFP Feature Register 0
Definition at line 530 of file core_cm7.h.
__IM uint32_t SCB_Type::MVFR1 |
Offset: 0x244 (R/ ) Media and VFP Feature Register 1
Definition at line 531 of file core_cm7.h.
__IM uint32_t SCB_Type::MVFR2 |
Offset: 0x248 (R/ ) Media and VFP Feature Register 1
Definition at line 532 of file core_cm7.h.
__IM uint32_t SCB_Type::PFR |
Offset: 0x040 (R/ ) Processor Feature Register
Definition at line 433 of file core_cm3.h.
__IOM uint32_t SCB_Type::SCR |
Offset: 0x010 (R/W) System Control Register
Definition at line 395 of file core_cm0.h.
__IOM uint32_t SCB_Type::SFCR |
Offset: 0x290 (R/W) Security Features Control Register
Definition at line 407 of file core_sc000.h.
__IOM uint32_t SCB_Type::SHCSR |
Offset: 0x024 (R/W) System Handler Control and State Register
Definition at line 399 of file core_cm0.h.
__IOM uint8_t SCB_Type::SHP |
Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
Definition at line 398 of file core_cm0.h.
__IOM uint8_t SCB_Type::SHP[12U] |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
Definition at line 425 of file core_cm3.h.
__IOM uint8_t SCB_Type::SHPR[12U] |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
Definition at line 508 of file core_cm7.h.
__OM uint32_t SCB_Type::STIR |
Offset: 0x200 ( /W) Software Triggered Interrupt Register
Definition at line 528 of file core_cm7.h.
__IOM uint32_t SCB_Type::VTOR |
Offset: 0x008 (R/W) Vector Table Offset Register
Definition at line 421 of file core_cm3.h.