51 #define UART0_RX_PORT (-1) 54 #define UART0_RX_PIN (-1) 56 #if UART0_RX_PORT >= 0 && UART0_RX_PIN < 0 || \ 57 UART0_RX_PORT < 0 && UART0_RX_PIN >= 0 58 #error Both UART0_RX_PORT and UART0_RX_PIN must be valid or invalid 62 #define UART0_TX_PORT (-1) 65 #define UART0_TX_PIN (-1) 67 #if UART0_TX_PORT >= 0 && UART0_TX_PIN < 0 || \ 68 UART0_TX_PORT < 0 && UART0_TX_PIN >= 0 69 #error Both UART0_TX_PORT and UART0_TX_PIN must be valid or invalid 72 #if UART0_RX_PORT >= 0 && UART0_TX_PORT < 0 || \ 73 UART0_RX_PORT < 0 && UART0_TX_PORT >= 0 74 #error Both UART0_RX and UART0_TX pads must be valid or invalid 77 #if UART_IN_USE(0) && UART0_RX_PORT < 0 78 #error Contiki is configured to use UART0, but its pads are not valid 82 #define UART1_RX_PORT (-1) 85 #define UART1_RX_PIN (-1) 87 #if UART1_RX_PORT >= 0 && UART1_RX_PIN < 0 || \ 88 UART1_RX_PORT < 0 && UART1_RX_PIN >= 0 89 #error Both UART1_RX_PORT and UART1_RX_PIN must be valid or invalid 93 #define UART1_TX_PORT (-1) 96 #define UART1_TX_PIN (-1) 98 #if UART1_TX_PORT >= 0 && UART1_TX_PIN < 0 || \ 99 UART1_TX_PORT < 0 && UART1_TX_PIN >= 0 100 #error Both UART1_TX_PORT and UART1_TX_PIN must be valid or invalid 103 #if UART1_RX_PORT >= 0 && UART1_TX_PORT < 0 || \ 104 UART1_RX_PORT < 0 && UART1_TX_PORT >= 0 105 #error Both UART1_RX and UART1_TX pads must be valid or invalid 108 #if UART_IN_USE(1) && UART1_RX_PORT < 0 109 #error Contiki is configured to use UART1, but its pads are not valid 112 #ifndef UART1_CTS_PORT 113 #define UART1_CTS_PORT (-1) 115 #ifndef UART1_CTS_PIN 116 #define UART1_CTS_PIN (-1) 118 #if UART1_CTS_PORT >= 0 && UART1_CTS_PIN < 0 || \ 119 UART1_CTS_PORT < 0 && UART1_CTS_PIN >= 0 120 #error Both UART1_CTS_PORT and UART1_CTS_PIN must be valid or invalid 123 #ifndef UART1_RTS_PORT 124 #define UART1_RTS_PORT (-1) 126 #ifndef UART1_RTS_PIN 127 #define UART1_RTS_PIN (-1) 129 #if UART1_RTS_PORT >= 0 && UART1_RTS_PIN < 0 || \ 130 UART1_RTS_PORT < 0 && UART1_RTS_PIN >= 0 131 #error Both UART1_RTS_PORT and UART1_RTS_PIN must be valid or invalid 138 #define UART_CLOCK_RATE SYS_CTRL_SYS_CLOCK 139 #define UART_CTL_HSE_VALUE 0 140 #define UART_CTL_VALUE (UART_CTL_RXE | UART_CTL_TXE | (UART_CTL_HSE_VALUE << 5)) 143 #define DIV_ROUND(num, denom) (((num) + (denom) / 2) / (denom)) 145 #define BAUD2BRD(baud) DIV_ROUND(UART_CLOCK_RATE << (UART_CTL_HSE_VALUE + 2), (baud)) 146 #define BAUD2IBRD(baud) (BAUD2BRD(baud) >> 6) 147 #define BAUD2FBRD(baud) (BAUD2BRD(baud) & 0x3f) 154 uint32_t sys_ctrl_rcgcuart_uart;
155 uint32_t sys_ctrl_scgcuart_uart;
156 uint32_t sys_ctrl_dcgcuart_uart;
158 uint32_t ioc_uartrxd_uart;
159 uint32_t ioc_pxx_sel_uart_txd;
169 static const uart_regs_t uart_regs[UART_INSTANCE_COUNT] = {
176 .ioc_pxx_sel_uart_txd = IOC_PXX_SEL_UART0_TXD,
179 .rx = {UART0_RX_PORT, UART0_RX_PIN},
180 .tx = {UART0_TX_PORT, UART0_TX_PIN},
190 .ioc_pxx_sel_uart_txd = IOC_PXX_SEL_UART1_TXD,
193 .rx = {UART1_RX_PORT, UART1_RX_PIN},
194 .tx = {UART1_TX_PORT, UART1_TX_PIN},
195 .cts = {UART1_CTS_PORT, UART1_CTS_PIN},
196 .rts = {UART1_RTS_PORT, UART1_RTS_PIN},
200 static int (* input_handler[UART_INSTANCE_COUNT])(
unsigned char c);
203 reset(uint32_t uart_base)
208 REG(uart_base +
UART_CTL) = UART_CTL_VALUE;
229 const uart_regs_t *regs;
231 for(regs = &uart_regs[0]; regs < &uart_regs[UART_INSTANCE_COUNT]; regs++) {
243 const uart_regs_t *regs;
245 if(uart >= UART_INSTANCE_COUNT) {
248 regs = &uart_regs[uart];
249 if(regs->rx.port < 0 || regs->tx.port < 0) {
253 lpm_register_peripheral(permit_pm1);
271 REG(regs->ioc_uartrxd_uart) = (regs->rx.port << 3) + regs->rx.pin;
278 ioc_set_sel(regs->tx.port, regs->tx.pin, regs->ioc_pxx_sel_uart_txd);
299 REG(regs->base +
UART_CTL) = UART_CTL_VALUE;
302 REG(regs->base +
UART_IBRD) = regs->ibrd;
303 REG(regs->base +
UART_FBRD) = regs->fbrd;
312 if(regs->cts.port >= 0) {
319 if(regs->rts.port >= 0) {
320 ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
336 if(uart >= UART_INSTANCE_COUNT) {
340 input_handler[uart] =
input;
348 if(uart >= UART_INSTANCE_COUNT) {
351 uart_base = uart_regs[uart].base;
360 uart_isr(uint8_t uart)
365 uart_base = uart_regs[uart].base;
369 mis = REG(uart_base +
UART_MIS) & 0x0000FFFF;
371 REG(uart_base +
UART_ICR) = 0x0000FFBF;
375 if(input_handler[uart] != NULL) {
376 input_handler[uart]((
unsigned char)(REG(uart_base +
UART_DR) & 0xFF));
380 mis = REG(uart_base +
UART_DR);
389 #define UART_ISR(u) void uart##u##_isr(void) { uart_isr(u); } #define UART_FR_TXFF
UART transmit FIFO full.
Header file for the cc2538 UART driver.
#define UART_FBRD
UART BAUD divisor: fractional.
#define UART_IM_RXIM
UART receive interrupt mask.
#define UART_IFLS
UART interrupt FIFO level.
#define SYS_CTRL_RCGCUART_UART0
UART0 Clock, CPU running.
Header file for the cc2538 System Control driver.
#define UART_LCRH
UART line control.
#define SYS_CTRL_RCGCUART
UART[1:0] clocks - active mode.
Header file with register and macro declarations for the cc2538 GPIO module.
#define UART_IFLS_RXIFLSEL_1_8
UART RX FIFO >= 1/8 full.
#define UART_MIS_BEMIS
UART break err masked stat.
void uart_init(uint8_t uart)
Initialises the UART controller, configures I/O control and interrupts.
#define UART_FR
UART flag.
#define UART_IFLS_TXIFLSEL_1_2
UART TX FIFO >= 1/2 empty.
Header file with declarations for the I/O Control module.
void uart_write_byte(uint8_t uart, uint8_t b)
Sends a single character down the UART.
#define UART_FR_BUSY
UART busy.
#define SYS_CTRL_DCGCUART_UART1
UART1 Clock, PM0.
Header file with register manipulation macro definitions.
#define UART_LCRH_FEN
UART enable FIFOs.
#define IOC_OVERRIDE_DIS
Override Disabled.
#define UART_IM_OEIM
UART overrun error mask.
#define GPIO_PIN_MASK(PIN)
Converts a pin number to a pin mask.
#define UART_CTL_UARTEN
UART enable.
#define IOC_UARTRXD_UART1
UART1 RX.
#define UART_CC
UART clock configuration.
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
#define UART_CTL_CTSEN
UART CTS flow-control enable (UART1 only)
#define UART_FR_RXFE
UART receive FIFO empty.
#define IOC_UARTCTS_UART1
UART1 CTS.
#define UART_MIS_FEMIS
UART framing err masked stat.
#define UART_ECR
UART RX status and err clear.
#define SYS_CTRL_DCGCUART
UART[1:0] clocks - PM0.
#define UART_ICR
UART interrupt clear.
#define UART_MIS_RTMIS
UART RX time-out masked stat.
#define UART_IM_FEIM
UART framing error.
void uart_set_input(uint8_t uart, int(*input)(unsigned char c))
Assigns a callback to be called when the UART receives a byte.
void ioc_set_over(uint8_t port, uint8_t pin, uint8_t over)
Set Port:Pin override function.
#define UART1_CONF_BAUD_RATE
Default UART1 baud rate.
#define SYS_CTRL_DCGCUART_UART0
UART0 Clock, PM0.
#define UART_MIS_OEMIS
UART overrun err masked stat.
#define SYS_CTRL_SCGCUART_UART1
UART1 Clock, CPU IDLE.
#define IOC_OVERRIDE_OE
Output Enable.
#define GPIO_PERIPHERAL_CONTROL(PORT_BASE, PIN_MASK)
Configure the pin to be under peripheral control with PIN_MASK of port with PORT_BASE.
#define UART_IBRD
UART BAUD divisor: integer.
#define ioc_input_sel(port, pin)
Generates an IOC_INPUT_SEL_PXn value from a port/pin number.
void ioc_set_sel(uint8_t port, uint8_t pin, uint8_t sel)
Function select for Port:Pin.
#define UART_CTL_RTSEN
UART RTS flow-control enable (UART1 only)
#define UART_MIS_RXMIS
UART RX masked intr stat.
#define UART_IM_RTIM
UART receive time-out mask.
#define UART_CTL
UART control.
#define SYS_CTRL_SCGCUART_UART0
UART0 Clock, CPU IDLE.
#define GPIO_PORT_TO_BASE(PORT)
Converts a port number to the port base address.
#define SYS_CTRL_RCGCUART_UART1
UART1 Clock, CPU running.
static void input(void)
Process a received 6lowpan packet.
#define UART_IM
UART interrupt mask.
#define IOC_UARTRXD_UART0
UART0 RX.
#define SYS_CTRL_SCGCUART
UART[1:0] clocks - sleep mode.
#define UART_MIS
UART masked interrupt status.
#define UART_DR
UART data.
#define UART_IM_BEIM
UART break error mask.
#define UART0_CONF_BAUD_RATE
Default UART0 baud rate.