63 new_hash(sha256_state_t *state,
const void *data,
void *hash)
84 if(state->final_digest) {
97 if(state->final_digest) {
119 return CRYPTO_DMA_BUS_ERROR;
130 return CRYPTO_SUCCESS;
159 if(state->final_digest) {
177 if(state->final_digest) {
186 if(state->final_digest) {
201 return CRYPTO_DMA_BUS_ERROR;
225 return CRYPTO_SUCCESS;
232 return CRYPTO_NULL_ERROR;
237 state->new_digest =
true;
238 state->final_digest =
false;
239 return CRYPTO_SUCCESS;
248 if(state == NULL || data == NULL) {
249 return CRYPTO_NULL_ERROR;
252 if(state->curlen >
sizeof(state->buf)) {
253 return CRYPTO_INVALID_PARAM;
257 return CRYPTO_RESOURCE_IN_USE;
260 if(len > 0 && state->new_digest) {
261 if(state->curlen == 0 && len > BLOCK_SIZE) {
262 rom_util_memcpy(state->buf, data, BLOCK_SIZE);
263 ret =
new_hash(state, state->buf, state->state);
264 if(ret != CRYPTO_SUCCESS) {
267 state->new_digest =
false;
268 state->length += BLOCK_SIZE << 3;
272 n = MIN(len, BLOCK_SIZE - state->curlen);
273 rom_util_memcpy(&state->buf[state->curlen], data, n);
277 if(state->curlen == BLOCK_SIZE && len > 0) {
278 ret =
new_hash(state, state->buf, state->state);
279 if(ret != CRYPTO_SUCCESS) {
282 state->new_digest =
false;
283 state->length += BLOCK_SIZE << 3;
289 while(len > 0 && !state->new_digest) {
290 if(state->curlen == 0 && len > BLOCK_SIZE) {
291 rom_util_memcpy(state->buf, data, BLOCK_SIZE);
292 ret =
resume_hash(state, state->buf, state->state);
293 if(ret != CRYPTO_SUCCESS) {
296 state->length += BLOCK_SIZE << 3;
300 n = MIN(len, BLOCK_SIZE - state->curlen);
301 rom_util_memcpy(&state->buf[state->curlen], data, n);
305 if(state->curlen == BLOCK_SIZE && len > 0) {
306 ret =
resume_hash(state, state->buf, state->state);
307 if(ret != CRYPTO_SUCCESS) {
310 state->length += BLOCK_SIZE << 3;
316 return CRYPTO_SUCCESS;
324 if(state == NULL || hash == NULL) {
325 return CRYPTO_NULL_ERROR;
328 if(state->curlen >
sizeof(state->buf)) {
329 return CRYPTO_INVALID_PARAM;
333 return CRYPTO_RESOURCE_IN_USE;
337 state->length += state->curlen << 3;
338 state->final_digest =
true;
339 if(state->new_digest) {
340 ret =
new_hash(state, state->buf, hash);
341 if(ret != CRYPTO_SUCCESS) {
346 if(ret != CRYPTO_SUCCESS) {
350 state->new_digest =
false;
351 state->final_digest =
false;
353 return CRYPTO_SUCCESS;
static uint8_t resume_hash(sha256_state_t *state, const void *data, void *hash)
Resumes an already started hash session in hardware.
#define AES_DMAC_CH0_CTRL
Channel 0 control.
#define AES_HASH_IO_BUF_CTRL
Input/output buffer control and status.
#define AES_HASH_LENGTH_IN_L
Hash length.
#define AES_AES_CTRL
AES input/output buffer control and mode.
#define AES_HASH_MODE_IN_NEW_HASH
New hash session.
#define AES_HASH_DIGEST_F
Hash digest.
#define AES_HASH_IO_BUF_CTRL_OUTPUT_FULL
Output buffer registers available.
#define AES_HASH_DIGEST_H
Hash digest.
#define AES_HASH_DIGEST_D
Hash digest.
uint8_t sha256_init(sha256_state_t *state)
Initializes the hash state.
#define AES_HASH_DIGEST_B
Hash digest.
Header file with register manipulation macro definitions.
#define AES_CTRL_INT_STAT_DMA_BUS_ERR
DMA bus error detected.
#define AES_CTRL_INT_CLR_DMA_BUS_ERR
Clear DMA bus error status.
#define AES_HASH_LENGTH_IN_H
Hash length.
#define AES_DMAC_CH1_CTRL
Channel 1 control.
#define AES_CTRL_INT_STAT_RESULT_AV
Result available interrupt status.
#define AES_CTRL_INT_CLR_RESULT_AV
Clear result available interrupt.
#define AES_CTRL_INT_CLR_DMA_IN_DONE
Clear DMA in done interrupt.
#define AES_HASH_MODE_IN_SHA256_MODE
Hash mode.
#define AES_CTRL_ALG_SEL_TAG
DMA operation includes TAG.
Header file for the cc2538 AES driver.
#define AES_CTRL_INT_CFG_LEVEL
Level interrupt type.
#define AES_CTRL_ALG_SEL
Algorithm select.
uint8_t sha256_process(sha256_state_t *state, const void *data, uint32_t len)
Processes a block of memory through the hash.
#define AES_CTRL_INT_CLR
Interrupt clear.
#define AES_CTRL_INT_EN_RESULT_AV
Result available interrupt enabled.
#define AES_CTRL_INT_EN_DMA_IN_DONE
DMA input done interrupt enabled.
#define AES_DMAC_CH0_EXTADDR
Channel 0 external address.
#define AES_DMAC_CH1_DMALENGTH
Channel 1 DMA length.
#define AES_HASH_IO_BUF_CTRL_PAD_DMA_MESSAGE
Hash engine message padding required.
#define AES_CTRL_INT_EN
Interrupt enable.
#define AES_DMAC_CH0_DMALENGTH
Channel 0 DMA length.
#define AES_HASH_DIGEST_C
Hash digest.
#define AES_CTRL_INT_STAT
Interrupt status.
#define AES_HASH_DIGEST_E
Hash digest.
Header file for the cc2538 ROM utility function library driver.
uint8_t sha256_done(sha256_state_t *state, void *hash)
Terminates hash session to get the digest.
#define AES_DMAC_CH_CTRL_EN
Channel enable.
#define AES_HASH_DIGEST_G
Hash digest.
static uint8_t new_hash(sha256_state_t *state, const void *data, void *hash)
Starts a new hash session in hardware.
Default definitions of C compiler quirk work-arounds.
#define AES_DMAC_CH1_EXTADDR
Channel 1 external address.
#define AES_HASH_MODE_IN
Hash mode.
#define AES_CTRL_ALG_SEL_HASH
Select hash engine as DMA destination.
#define AES_CTRL_INT_CFG
Interrupt configuration.
Header file for the cc2538 SHA-256 driver.
#define AES_HASH_DIGEST_A
Hash digest.