35 #if defined ( __ICCARM__ ) 36 #pragma system_include 37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 38 #pragma clang system_header 41 #ifndef __CORE_SC000_H_GENERIC 42 #define __CORE_SC000_H_GENERIC 74 #define __SC000_CMSIS_VERSION_MAIN (0x04U) 75 #define __SC000_CMSIS_VERSION_SUB (0x1EU) 76 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ 77 __SC000_CMSIS_VERSION_SUB ) 79 #define __CORTEX_SC (000U) 82 #if defined ( __CC_ARM ) 84 #define __INLINE __inline 85 #define __STATIC_INLINE static __inline 87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89 #define __INLINE __inline 90 #define __STATIC_INLINE static __inline 92 #elif defined ( __GNUC__ ) 94 #define __INLINE inline 95 #define __STATIC_INLINE static inline 97 #elif defined ( __ICCARM__ ) 99 #define __INLINE inline 100 #define __STATIC_INLINE static inline 102 #elif defined ( __TMS470__ ) 104 #define __STATIC_INLINE static inline 106 #elif defined ( __TASKING__ ) 108 #define __INLINE inline 109 #define __STATIC_INLINE static inline 111 #elif defined ( __CSMC__ ) 114 #define __INLINE inline 115 #define __STATIC_INLINE static inline 118 #error Unknown compiler 124 #define __FPU_USED 0U 126 #if defined ( __CC_ARM ) 127 #if defined __TARGET_FPU_VFP 128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 132 #if defined __ARM_PCS_VFP 133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 136 #elif defined ( __GNUC__ ) 137 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 141 #elif defined ( __ICCARM__ ) 142 #if defined __ARMVFP__ 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 146 #elif defined ( __TMS470__ ) 147 #if defined __TI_VFP_SUPPORT__ 148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 151 #elif defined ( __TASKING__ ) 152 #if defined __FPU_VFP__ 153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 156 #elif defined ( __CSMC__ ) 157 #if ( __CSMC__ & 0x400U) 158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 172 #ifndef __CMSIS_GENERIC 174 #ifndef __CORE_SC000_H_DEPENDANT 175 #define __CORE_SC000_H_DEPENDANT 182 #if defined __CHECK_DEVICE_DEFINES 184 #define __SC000_REV 0x0000U 185 #warning "__SC000_REV not defined in device header file; using default!" 188 #ifndef __MPU_PRESENT 189 #define __MPU_PRESENT 0U 190 #warning "__MPU_PRESENT not defined in device header file; using default!" 193 #ifndef __NVIC_PRIO_BITS 194 #define __NVIC_PRIO_BITS 2U 195 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 198 #ifndef __Vendor_SysTickConfig 199 #define __Vendor_SysTickConfig 0U 200 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 215 #define __I volatile const 218 #define __IO volatile 221 #define __IM volatile const 222 #define __OM volatile 223 #define __IOM volatile 257 uint32_t _reserved0:28;
267 #define APSR_N_Pos 31U 268 #define APSR_N_Msk (1UL << APSR_N_Pos) 270 #define APSR_Z_Pos 30U 271 #define APSR_Z_Msk (1UL << APSR_Z_Pos) 273 #define APSR_C_Pos 29U 274 #define APSR_C_Msk (1UL << APSR_C_Pos) 276 #define APSR_V_Pos 28U 277 #define APSR_V_Msk (1UL << APSR_V_Pos) 288 uint32_t _reserved0:23;
294 #define IPSR_ISR_Pos 0U 295 #define IPSR_ISR_Msk (0x1FFUL ) 306 uint32_t _reserved0:15;
308 uint32_t _reserved1:3;
318 #define xPSR_N_Pos 31U 319 #define xPSR_N_Msk (1UL << xPSR_N_Pos) 321 #define xPSR_Z_Pos 30U 322 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) 324 #define xPSR_C_Pos 29U 325 #define xPSR_C_Msk (1UL << xPSR_C_Pos) 327 #define xPSR_V_Pos 28U 328 #define xPSR_V_Msk (1UL << xPSR_V_Pos) 330 #define xPSR_T_Pos 24U 331 #define xPSR_T_Msk (1UL << xPSR_T_Pos) 333 #define xPSR_ISR_Pos 0U 334 #define xPSR_ISR_Msk (0x1FFUL ) 344 uint32_t _reserved0:1;
346 uint32_t _reserved1:30;
352 #define CONTROL_SPSEL_Pos 1U 353 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) 370 __IOM uint32_t ISER[1U];
371 uint32_t RESERVED0[31U];
372 __IOM uint32_t ICER[1U];
373 uint32_t RSERVED1[31U];
374 __IOM uint32_t ISPR[1U];
375 uint32_t RESERVED2[31U];
376 __IOM uint32_t ICPR[1U];
377 uint32_t RESERVED3[31U];
378 uint32_t RESERVED4[64U];
379 __IOM uint32_t IP[8U];
400 __IOM uint32_t AIRCR;
403 uint32_t RESERVED0[1U];
404 __IOM uint32_t SHP[2U];
405 __IOM uint32_t SHCSR;
406 uint32_t RESERVED1[154U];
411 #define SCB_CPUID_IMPLEMENTER_Pos 24U 412 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 414 #define SCB_CPUID_VARIANT_Pos 20U 415 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 417 #define SCB_CPUID_ARCHITECTURE_Pos 16U 418 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 420 #define SCB_CPUID_PARTNO_Pos 4U 421 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 423 #define SCB_CPUID_REVISION_Pos 0U 424 #define SCB_CPUID_REVISION_Msk (0xFUL ) 427 #define SCB_ICSR_NMIPENDSET_Pos 31U 428 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 430 #define SCB_ICSR_PENDSVSET_Pos 28U 431 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 433 #define SCB_ICSR_PENDSVCLR_Pos 27U 434 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 436 #define SCB_ICSR_PENDSTSET_Pos 26U 437 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 439 #define SCB_ICSR_PENDSTCLR_Pos 25U 440 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 442 #define SCB_ICSR_ISRPREEMPT_Pos 23U 443 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 445 #define SCB_ICSR_ISRPENDING_Pos 22U 446 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 448 #define SCB_ICSR_VECTPENDING_Pos 12U 449 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 451 #define SCB_ICSR_VECTACTIVE_Pos 0U 452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) 455 #define SCB_VTOR_TBLOFF_Pos 7U 456 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 459 #define SCB_AIRCR_VECTKEY_Pos 16U 460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U 463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 465 #define SCB_AIRCR_ENDIANESS_Pos 15U 466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 468 #define SCB_AIRCR_SYSRESETREQ_Pos 2U 469 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 471 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U 472 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 475 #define SCB_SCR_SEVONPEND_Pos 4U 476 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 478 #define SCB_SCR_SLEEPDEEP_Pos 2U 479 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 481 #define SCB_SCR_SLEEPONEXIT_Pos 1U 482 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 485 #define SCB_CCR_STKALIGN_Pos 9U 486 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 488 #define SCB_CCR_UNALIGN_TRP_Pos 3U 489 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 492 #define SCB_SHCSR_SVCALLPENDED_Pos 15U 493 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 510 uint32_t RESERVED0[2U];
511 __IOM uint32_t ACTLR;
515 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U 516 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL ) 540 #define SysTick_CTRL_COUNTFLAG_Pos 16U 541 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 543 #define SysTick_CTRL_CLKSOURCE_Pos 2U 544 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 546 #define SysTick_CTRL_TICKINT_Pos 1U 547 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 549 #define SysTick_CTRL_ENABLE_Pos 0U 550 #define SysTick_CTRL_ENABLE_Msk (1UL ) 553 #define SysTick_LOAD_RELOAD_Pos 0U 554 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) 557 #define SysTick_VAL_CURRENT_Pos 0U 558 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) 561 #define SysTick_CALIB_NOREF_Pos 31U 562 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 564 #define SysTick_CALIB_SKEW_Pos 30U 565 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 567 #define SysTick_CALIB_TENMS_Pos 0U 568 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) 572 #if (__MPU_PRESENT == 1U) 593 #define MPU_TYPE_IREGION_Pos 16U 594 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 596 #define MPU_TYPE_DREGION_Pos 8U 597 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 599 #define MPU_TYPE_SEPARATE_Pos 0U 600 #define MPU_TYPE_SEPARATE_Msk (1UL ) 603 #define MPU_CTRL_PRIVDEFENA_Pos 2U 604 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 606 #define MPU_CTRL_HFNMIENA_Pos 1U 607 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 609 #define MPU_CTRL_ENABLE_Pos 0U 610 #define MPU_CTRL_ENABLE_Msk (1UL ) 613 #define MPU_RNR_REGION_Pos 0U 614 #define MPU_RNR_REGION_Msk (0xFFUL ) 617 #define MPU_RBAR_ADDR_Pos 8U 618 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) 620 #define MPU_RBAR_VALID_Pos 4U 621 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 623 #define MPU_RBAR_REGION_Pos 0U 624 #define MPU_RBAR_REGION_Msk (0xFUL ) 627 #define MPU_RASR_ATTRS_Pos 16U 628 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 630 #define MPU_RASR_XN_Pos 28U 631 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) 633 #define MPU_RASR_AP_Pos 24U 634 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) 636 #define MPU_RASR_TEX_Pos 19U 637 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) 639 #define MPU_RASR_S_Pos 18U 640 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) 642 #define MPU_RASR_C_Pos 17U 643 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) 645 #define MPU_RASR_B_Pos 16U 646 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) 648 #define MPU_RASR_SRD_Pos 8U 649 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 651 #define MPU_RASR_SIZE_Pos 1U 652 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 654 #define MPU_RASR_ENABLE_Pos 0U 655 #define MPU_RASR_ENABLE_Msk (1UL ) 684 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) 692 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) 705 #define SCS_BASE (0xE000E000UL) 706 #define SysTick_BASE (SCS_BASE + 0x0010UL) 707 #define NVIC_BASE (SCS_BASE + 0x0100UL) 708 #define SCB_BASE (SCS_BASE + 0x0D00UL) 710 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 711 #define SCB ((SCB_Type *) SCB_BASE ) 712 #define SysTick ((SysTick_Type *) SysTick_BASE ) 713 #define NVIC ((NVIC_Type *) NVIC_BASE ) 715 #if (__MPU_PRESENT == 1U) 716 #define MPU_BASE (SCS_BASE + 0x0D90UL) 717 #define MPU ((MPU_Type *) MPU_BASE ) 747 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 748 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 749 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 759 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
770 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
783 return((uint32_t)(((
NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
794 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
805 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
818 if ((int32_t)(IRQn) < 0)
820 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(
SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
821 (((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
825 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(
NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
826 (((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
843 if ((int32_t)(IRQn) < 0)
845 return((uint32_t)(((
SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
__NVIC_PRIO_BITS)));
849 return((uint32_t)(((
NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
__NVIC_PRIO_BITS)));
884 #if (__Vendor_SysTickConfig == 0U) 904 SysTick->LOAD = (uint32_t)(ticks - 1UL);
CMSIS Cortex-M Core Function Access Header File.
#define SCB_AIRCR_VECTKEY_Pos
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
#define SysTick_CTRL_CLKSOURCE_Msk
Structure type to access the System Control Block (SCB).
CMSIS Cortex-M Core Instruction Access Header File.
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
#define SysTick_CTRL_TICKINT_Msk
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Structure type to access the System Timer (SysTick).
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Union type to access the Application Program Status Register (APSR).
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
__STATIC_INLINE void __NOP(void)
No Operation.
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Union type to access the Control Registers (CONTROL).
#define SysTick_LOAD_RELOAD_Msk
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Union type to access the Interrupt Program Status Register (IPSR).
Union type to access the Special-Purpose Program Status Registers (xPSR).
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
#define SysTick_CTRL_ENABLE_Msk
#define __NVIC_PRIO_BITS
Number of Bits used for Priority Levels.
#define SCB_AIRCR_SYSRESETREQ_Msk