35 #if defined ( __ICCARM__ ) 36 #pragma system_include 37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 38 #pragma clang system_header 41 #ifndef __CORE_CM7_H_GENERIC 42 #define __CORE_CM7_H_GENERIC 74 #define __CM7_CMSIS_VERSION_MAIN (0x04U) 75 #define __CM7_CMSIS_VERSION_SUB (0x1EU) 76 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 77 __CM7_CMSIS_VERSION_SUB ) 79 #define __CORTEX_M (0x07U) 82 #if defined ( __CC_ARM ) 84 #define __INLINE __inline 85 #define __STATIC_INLINE static __inline 87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89 #define __INLINE __inline 90 #define __STATIC_INLINE static __inline 92 #elif defined ( __GNUC__ ) 94 #define __INLINE inline 95 #define __STATIC_INLINE static inline 97 #elif defined ( __ICCARM__ ) 99 #define __INLINE inline 100 #define __STATIC_INLINE static inline 102 #elif defined ( __TMS470__ ) 104 #define __STATIC_INLINE static inline 106 #elif defined ( __TASKING__ ) 108 #define __INLINE inline 109 #define __STATIC_INLINE static inline 111 #elif defined ( __CSMC__ ) 114 #define __INLINE inline 115 #define __STATIC_INLINE static inline 118 #error Unknown compiler 124 #if defined ( __CC_ARM ) 125 #if defined __TARGET_FPU_VFP 126 #if (__FPU_PRESENT == 1U) 127 #define __FPU_USED 1U 129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 130 #define __FPU_USED 0U 133 #define __FPU_USED 0U 136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 137 #if defined __ARM_PCS_VFP 138 #if (__FPU_PRESENT == 1) 139 #define __FPU_USED 1U 141 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 142 #define __FPU_USED 0U 145 #define __FPU_USED 0U 148 #elif defined ( __GNUC__ ) 149 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 150 #if (__FPU_PRESENT == 1U) 151 #define __FPU_USED 1U 153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 154 #define __FPU_USED 0U 157 #define __FPU_USED 0U 160 #elif defined ( __ICCARM__ ) 161 #if defined __ARMVFP__ 162 #if (__FPU_PRESENT == 1U) 163 #define __FPU_USED 1U 165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 166 #define __FPU_USED 0U 169 #define __FPU_USED 0U 172 #elif defined ( __TMS470__ ) 173 #if defined __TI_VFP_SUPPORT__ 174 #if (__FPU_PRESENT == 1U) 175 #define __FPU_USED 1U 177 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 178 #define __FPU_USED 0U 181 #define __FPU_USED 0U 184 #elif defined ( __TASKING__ ) 185 #if defined __FPU_VFP__ 186 #if (__FPU_PRESENT == 1U) 187 #define __FPU_USED 1U 189 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 190 #define __FPU_USED 0U 193 #define __FPU_USED 0U 196 #elif defined ( __CSMC__ ) 197 #if ( __CSMC__ & 0x400U) 198 #if (__FPU_PRESENT == 1U) 199 #define __FPU_USED 1U 201 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 202 #define __FPU_USED 0U 205 #define __FPU_USED 0U 220 #ifndef __CMSIS_GENERIC 222 #ifndef __CORE_CM7_H_DEPENDANT 223 #define __CORE_CM7_H_DEPENDANT 230 #if defined __CHECK_DEVICE_DEFINES 232 #define __CM7_REV 0x0000U 233 #warning "__CM7_REV not defined in device header file; using default!" 236 #ifndef __FPU_PRESENT 237 #define __FPU_PRESENT 0U 238 #warning "__FPU_PRESENT not defined in device header file; using default!" 241 #ifndef __MPU_PRESENT 242 #define __MPU_PRESENT 0U 243 #warning "__MPU_PRESENT not defined in device header file; using default!" 246 #ifndef __ICACHE_PRESENT 247 #define __ICACHE_PRESENT 0U 248 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 251 #ifndef __DCACHE_PRESENT 252 #define __DCACHE_PRESENT 0U 253 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 256 #ifndef __DTCM_PRESENT 257 #define __DTCM_PRESENT 0U 258 #warning "__DTCM_PRESENT not defined in device header file; using default!" 261 #ifndef __NVIC_PRIO_BITS 262 #define __NVIC_PRIO_BITS 3U 263 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 266 #ifndef __Vendor_SysTickConfig 267 #define __Vendor_SysTickConfig 0U 268 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 283 #define __I volatile const 286 #define __IO volatile 289 #define __IM volatile const 290 #define __OM volatile 291 #define __IOM volatile 327 uint32_t _reserved0:16;
329 uint32_t _reserved1:7;
340 #define APSR_N_Pos 31U 341 #define APSR_N_Msk (1UL << APSR_N_Pos) 343 #define APSR_Z_Pos 30U 344 #define APSR_Z_Msk (1UL << APSR_Z_Pos) 346 #define APSR_C_Pos 29U 347 #define APSR_C_Msk (1UL << APSR_C_Pos) 349 #define APSR_V_Pos 28U 350 #define APSR_V_Msk (1UL << APSR_V_Pos) 352 #define APSR_Q_Pos 27U 353 #define APSR_Q_Msk (1UL << APSR_Q_Pos) 355 #define APSR_GE_Pos 16U 356 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) 367 uint32_t _reserved0:23;
373 #define IPSR_ISR_Pos 0U 374 #define IPSR_ISR_Msk (0x1FFUL ) 385 uint32_t _reserved0:7;
387 uint32_t _reserved1:4;
400 #define xPSR_N_Pos 31U 401 #define xPSR_N_Msk (1UL << xPSR_N_Pos) 403 #define xPSR_Z_Pos 30U 404 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) 406 #define xPSR_C_Pos 29U 407 #define xPSR_C_Msk (1UL << xPSR_C_Pos) 409 #define xPSR_V_Pos 28U 410 #define xPSR_V_Msk (1UL << xPSR_V_Pos) 412 #define xPSR_Q_Pos 27U 413 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) 415 #define xPSR_IT_Pos 25U 416 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) 418 #define xPSR_T_Pos 24U 419 #define xPSR_T_Msk (1UL << xPSR_T_Pos) 421 #define xPSR_GE_Pos 16U 422 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) 424 #define xPSR_ISR_Pos 0U 425 #define xPSR_ISR_Msk (0x1FFUL ) 438 uint32_t _reserved0:29;
444 #define CONTROL_FPCA_Pos 2U 445 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) 447 #define CONTROL_SPSEL_Pos 1U 448 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) 450 #define CONTROL_nPRIV_Pos 0U 451 #define CONTROL_nPRIV_Msk (1UL ) 468 __IOM uint32_t ISER[8U];
469 uint32_t RESERVED0[24U];
470 __IOM uint32_t ICER[8U];
471 uint32_t RSERVED1[24U];
472 __IOM uint32_t ISPR[8U];
473 uint32_t RESERVED2[24U];
474 __IOM uint32_t ICPR[8U];
475 uint32_t RESERVED3[24U];
476 __IOM uint32_t IABR[8U];
477 uint32_t RESERVED4[56U];
478 __IOM uint8_t IP[240U];
479 uint32_t RESERVED5[644U];
484 #define NVIC_STIR_INTID_Pos 0U 485 #define NVIC_STIR_INTID_Msk (0x1FFUL ) 505 __IOM uint32_t AIRCR;
508 __IOM uint8_t SHPR[12U];
509 __IOM uint32_t SHCSR;
513 __IOM uint32_t MMFAR;
516 __IM uint32_t ID_PFR[2U];
517 __IM uint32_t ID_DFR;
518 __IM uint32_t ID_AFR;
519 __IM uint32_t ID_MFR[4U];
520 __IM uint32_t ID_ISAR[5U];
521 uint32_t RESERVED0[1U];
524 __IM uint32_t CCSIDR;
525 __IOM uint32_t CSSELR;
526 __IOM uint32_t CPACR;
527 uint32_t RESERVED3[93U];
529 uint32_t RESERVED4[15U];
533 uint32_t RESERVED5[1U];
534 __OM uint32_t ICIALLU;
535 uint32_t RESERVED6[1U];
536 __OM uint32_t ICIMVAU;
537 __OM uint32_t DCIMVAC;
539 __OM uint32_t DCCMVAU;
540 __OM uint32_t DCCMVAC;
542 __OM uint32_t DCCIMVAC;
543 __OM uint32_t DCCISW;
544 uint32_t RESERVED7[6U];
545 __IOM uint32_t ITCMCR;
546 __IOM uint32_t DTCMCR;
547 __IOM uint32_t AHBPCR;
549 __IOM uint32_t AHBSCR;
550 uint32_t RESERVED8[1U];
551 __IOM uint32_t ABFSR;
555 #define SCB_CPUID_IMPLEMENTER_Pos 24U 556 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 558 #define SCB_CPUID_VARIANT_Pos 20U 559 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 561 #define SCB_CPUID_ARCHITECTURE_Pos 16U 562 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 564 #define SCB_CPUID_PARTNO_Pos 4U 565 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 567 #define SCB_CPUID_REVISION_Pos 0U 568 #define SCB_CPUID_REVISION_Msk (0xFUL ) 571 #define SCB_ICSR_NMIPENDSET_Pos 31U 572 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 574 #define SCB_ICSR_PENDSVSET_Pos 28U 575 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 577 #define SCB_ICSR_PENDSVCLR_Pos 27U 578 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 580 #define SCB_ICSR_PENDSTSET_Pos 26U 581 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 583 #define SCB_ICSR_PENDSTCLR_Pos 25U 584 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 586 #define SCB_ICSR_ISRPREEMPT_Pos 23U 587 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 589 #define SCB_ICSR_ISRPENDING_Pos 22U 590 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 592 #define SCB_ICSR_VECTPENDING_Pos 12U 593 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 595 #define SCB_ICSR_RETTOBASE_Pos 11U 596 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) 598 #define SCB_ICSR_VECTACTIVE_Pos 0U 599 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) 602 #define SCB_VTOR_TBLOFF_Pos 7U 603 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 606 #define SCB_AIRCR_VECTKEY_Pos 16U 607 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 609 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U 610 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 612 #define SCB_AIRCR_ENDIANESS_Pos 15U 613 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 615 #define SCB_AIRCR_PRIGROUP_Pos 8U 616 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) 618 #define SCB_AIRCR_SYSRESETREQ_Pos 2U 619 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 621 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U 622 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 624 #define SCB_AIRCR_VECTRESET_Pos 0U 625 #define SCB_AIRCR_VECTRESET_Msk (1UL ) 628 #define SCB_SCR_SEVONPEND_Pos 4U 629 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 631 #define SCB_SCR_SLEEPDEEP_Pos 2U 632 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 634 #define SCB_SCR_SLEEPONEXIT_Pos 1U 635 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 638 #define SCB_CCR_BP_Pos 18U 639 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) 641 #define SCB_CCR_IC_Pos 17U 642 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) 644 #define SCB_CCR_DC_Pos 16U 645 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) 647 #define SCB_CCR_STKALIGN_Pos 9U 648 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 650 #define SCB_CCR_BFHFNMIGN_Pos 8U 651 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) 653 #define SCB_CCR_DIV_0_TRP_Pos 4U 654 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) 656 #define SCB_CCR_UNALIGN_TRP_Pos 3U 657 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 659 #define SCB_CCR_USERSETMPEND_Pos 1U 660 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) 662 #define SCB_CCR_NONBASETHRDENA_Pos 0U 663 #define SCB_CCR_NONBASETHRDENA_Msk (1UL ) 666 #define SCB_SHCSR_USGFAULTENA_Pos 18U 667 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) 669 #define SCB_SHCSR_BUSFAULTENA_Pos 17U 670 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) 672 #define SCB_SHCSR_MEMFAULTENA_Pos 16U 673 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) 675 #define SCB_SHCSR_SVCALLPENDED_Pos 15U 676 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 678 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U 679 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) 681 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U 682 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) 684 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U 685 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) 687 #define SCB_SHCSR_SYSTICKACT_Pos 11U 688 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) 690 #define SCB_SHCSR_PENDSVACT_Pos 10U 691 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) 693 #define SCB_SHCSR_MONITORACT_Pos 8U 694 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) 696 #define SCB_SHCSR_SVCALLACT_Pos 7U 697 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) 699 #define SCB_SHCSR_USGFAULTACT_Pos 3U 700 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) 702 #define SCB_SHCSR_BUSFAULTACT_Pos 1U 703 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) 705 #define SCB_SHCSR_MEMFAULTACT_Pos 0U 706 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL ) 709 #define SCB_CFSR_USGFAULTSR_Pos 16U 710 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) 712 #define SCB_CFSR_BUSFAULTSR_Pos 8U 713 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) 715 #define SCB_CFSR_MEMFAULTSR_Pos 0U 716 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL ) 719 #define SCB_HFSR_DEBUGEVT_Pos 31U 720 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) 722 #define SCB_HFSR_FORCED_Pos 30U 723 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) 725 #define SCB_HFSR_VECTTBL_Pos 1U 726 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) 729 #define SCB_DFSR_EXTERNAL_Pos 4U 730 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) 732 #define SCB_DFSR_VCATCH_Pos 3U 733 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) 735 #define SCB_DFSR_DWTTRAP_Pos 2U 736 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) 738 #define SCB_DFSR_BKPT_Pos 1U 739 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) 741 #define SCB_DFSR_HALTED_Pos 0U 742 #define SCB_DFSR_HALTED_Msk (1UL ) 745 #define SCB_CLIDR_LOUU_Pos 27U 746 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) 748 #define SCB_CLIDR_LOC_Pos 24U 749 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) 752 #define SCB_CTR_FORMAT_Pos 29U 753 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) 755 #define SCB_CTR_CWG_Pos 24U 756 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) 758 #define SCB_CTR_ERG_Pos 20U 759 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) 761 #define SCB_CTR_DMINLINE_Pos 16U 762 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) 764 #define SCB_CTR_IMINLINE_Pos 0U 765 #define SCB_CTR_IMINLINE_Msk (0xFUL ) 768 #define SCB_CCSIDR_WT_Pos 31U 769 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) 771 #define SCB_CCSIDR_WB_Pos 30U 772 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) 774 #define SCB_CCSIDR_RA_Pos 29U 775 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) 777 #define SCB_CCSIDR_WA_Pos 28U 778 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) 780 #define SCB_CCSIDR_NUMSETS_Pos 13U 781 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) 783 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U 784 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) 786 #define SCB_CCSIDR_LINESIZE_Pos 0U 787 #define SCB_CCSIDR_LINESIZE_Msk (7UL ) 790 #define SCB_CSSELR_LEVEL_Pos 1U 791 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) 793 #define SCB_CSSELR_IND_Pos 0U 794 #define SCB_CSSELR_IND_Msk (1UL ) 797 #define SCB_STIR_INTID_Pos 0U 798 #define SCB_STIR_INTID_Msk (0x1FFUL ) 801 #define SCB_DCISW_WAY_Pos 30U 802 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) 804 #define SCB_DCISW_SET_Pos 5U 805 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) 808 #define SCB_DCCSW_WAY_Pos 30U 809 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) 811 #define SCB_DCCSW_SET_Pos 5U 812 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) 815 #define SCB_DCCISW_WAY_Pos 30U 816 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) 818 #define SCB_DCCISW_SET_Pos 5U 819 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) 822 #define SCB_ITCMCR_SZ_Pos 3U 823 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) 825 #define SCB_ITCMCR_RETEN_Pos 2U 826 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) 828 #define SCB_ITCMCR_RMW_Pos 1U 829 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) 831 #define SCB_ITCMCR_EN_Pos 0U 832 #define SCB_ITCMCR_EN_Msk (1UL ) 835 #define SCB_DTCMCR_SZ_Pos 3U 836 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) 838 #define SCB_DTCMCR_RETEN_Pos 2U 839 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) 841 #define SCB_DTCMCR_RMW_Pos 1U 842 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) 844 #define SCB_DTCMCR_EN_Pos 0U 845 #define SCB_DTCMCR_EN_Msk (1UL ) 848 #define SCB_AHBPCR_SZ_Pos 1U 849 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) 851 #define SCB_AHBPCR_EN_Pos 0U 852 #define SCB_AHBPCR_EN_Msk (1UL ) 855 #define SCB_CACR_FORCEWT_Pos 2U 856 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) 858 #define SCB_CACR_ECCEN_Pos 1U 859 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) 861 #define SCB_CACR_SIWT_Pos 0U 862 #define SCB_CACR_SIWT_Msk (1UL ) 865 #define SCB_AHBSCR_INITCOUNT_Pos 11U 866 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) 868 #define SCB_AHBSCR_TPRI_Pos 2U 869 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) 871 #define SCB_AHBSCR_CTL_Pos 0U 872 #define SCB_AHBSCR_CTL_Msk (3UL ) 875 #define SCB_ABFSR_AXIMTYPE_Pos 8U 876 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) 878 #define SCB_ABFSR_EPPB_Pos 4U 879 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) 881 #define SCB_ABFSR_AXIM_Pos 3U 882 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) 884 #define SCB_ABFSR_AHBP_Pos 2U 885 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) 887 #define SCB_ABFSR_DTCM_Pos 1U 888 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) 890 #define SCB_ABFSR_ITCM_Pos 0U 891 #define SCB_ABFSR_ITCM_Msk (1UL ) 908 uint32_t RESERVED0[1U];
910 __IOM uint32_t ACTLR;
914 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U 915 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL ) 918 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U 919 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) 921 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U 922 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) 924 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U 925 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) 927 #define SCnSCB_ACTLR_DISFOLD_Pos 2U 928 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) 930 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U 931 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL ) 955 #define SysTick_CTRL_COUNTFLAG_Pos 16U 956 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 958 #define SysTick_CTRL_CLKSOURCE_Pos 2U 959 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 961 #define SysTick_CTRL_TICKINT_Pos 1U 962 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 964 #define SysTick_CTRL_ENABLE_Pos 0U 965 #define SysTick_CTRL_ENABLE_Msk (1UL ) 968 #define SysTick_LOAD_RELOAD_Pos 0U 969 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) 972 #define SysTick_VAL_CURRENT_Pos 0U 973 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) 976 #define SysTick_CALIB_NOREF_Pos 31U 977 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 979 #define SysTick_CALIB_SKEW_Pos 30U 980 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 982 #define SysTick_CALIB_TENMS_Pos 0U 983 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) 1006 uint32_t RESERVED0[864U];
1008 uint32_t RESERVED1[15U];
1010 uint32_t RESERVED2[15U];
1012 uint32_t RESERVED3[29U];
1015 __IOM uint32_t IMCR;
1016 uint32_t RESERVED4[43U];
1019 uint32_t RESERVED5[6U];
1035 #define ITM_TPR_PRIVMASK_Pos 0U 1036 #define ITM_TPR_PRIVMASK_Msk (0xFUL ) 1039 #define ITM_TCR_BUSY_Pos 23U 1040 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) 1042 #define ITM_TCR_TraceBusID_Pos 16U 1043 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) 1045 #define ITM_TCR_GTSFREQ_Pos 10U 1046 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) 1048 #define ITM_TCR_TSPrescale_Pos 8U 1049 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) 1051 #define ITM_TCR_SWOENA_Pos 4U 1052 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) 1054 #define ITM_TCR_DWTENA_Pos 3U 1055 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) 1057 #define ITM_TCR_SYNCENA_Pos 2U 1058 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) 1060 #define ITM_TCR_TSENA_Pos 1U 1061 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) 1063 #define ITM_TCR_ITMENA_Pos 0U 1064 #define ITM_TCR_ITMENA_Msk (1UL ) 1067 #define ITM_IWR_ATVALIDM_Pos 0U 1068 #define ITM_IWR_ATVALIDM_Msk (1UL ) 1071 #define ITM_IRR_ATREADYM_Pos 0U 1072 #define ITM_IRR_ATREADYM_Msk (1UL ) 1075 #define ITM_IMCR_INTEGRATION_Pos 0U 1076 #define ITM_IMCR_INTEGRATION_Msk (1UL ) 1079 #define ITM_LSR_ByteAcc_Pos 2U 1080 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) 1082 #define ITM_LSR_Access_Pos 1U 1083 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) 1085 #define ITM_LSR_Present_Pos 0U 1086 #define ITM_LSR_Present_Msk (1UL ) 1103 __IOM uint32_t CTRL;
1104 __IOM uint32_t CYCCNT;
1105 __IOM uint32_t CPICNT;
1106 __IOM uint32_t EXCCNT;
1107 __IOM uint32_t SLEEPCNT;
1108 __IOM uint32_t LSUCNT;
1109 __IOM uint32_t FOLDCNT;
1111 __IOM uint32_t COMP0;
1112 __IOM uint32_t MASK0;
1113 __IOM uint32_t FUNCTION0;
1114 uint32_t RESERVED0[1U];
1115 __IOM uint32_t COMP1;
1116 __IOM uint32_t MASK1;
1117 __IOM uint32_t FUNCTION1;
1118 uint32_t RESERVED1[1U];
1119 __IOM uint32_t COMP2;
1120 __IOM uint32_t MASK2;
1121 __IOM uint32_t FUNCTION2;
1122 uint32_t RESERVED2[1U];
1123 __IOM uint32_t COMP3;
1124 __IOM uint32_t MASK3;
1125 __IOM uint32_t FUNCTION3;
1126 uint32_t RESERVED3[981U];
1132 #define DWT_CTRL_NUMCOMP_Pos 28U 1133 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) 1135 #define DWT_CTRL_NOTRCPKT_Pos 27U 1136 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) 1138 #define DWT_CTRL_NOEXTTRIG_Pos 26U 1139 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) 1141 #define DWT_CTRL_NOCYCCNT_Pos 25U 1142 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) 1144 #define DWT_CTRL_NOPRFCNT_Pos 24U 1145 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) 1147 #define DWT_CTRL_CYCEVTENA_Pos 22U 1148 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) 1150 #define DWT_CTRL_FOLDEVTENA_Pos 21U 1151 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) 1153 #define DWT_CTRL_LSUEVTENA_Pos 20U 1154 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) 1156 #define DWT_CTRL_SLEEPEVTENA_Pos 19U 1157 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) 1159 #define DWT_CTRL_EXCEVTENA_Pos 18U 1160 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) 1162 #define DWT_CTRL_CPIEVTENA_Pos 17U 1163 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) 1165 #define DWT_CTRL_EXCTRCENA_Pos 16U 1166 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) 1168 #define DWT_CTRL_PCSAMPLENA_Pos 12U 1169 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) 1171 #define DWT_CTRL_SYNCTAP_Pos 10U 1172 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) 1174 #define DWT_CTRL_CYCTAP_Pos 9U 1175 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) 1177 #define DWT_CTRL_POSTINIT_Pos 5U 1178 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) 1180 #define DWT_CTRL_POSTPRESET_Pos 1U 1181 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) 1183 #define DWT_CTRL_CYCCNTENA_Pos 0U 1184 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL ) 1187 #define DWT_CPICNT_CPICNT_Pos 0U 1188 #define DWT_CPICNT_CPICNT_Msk (0xFFUL ) 1191 #define DWT_EXCCNT_EXCCNT_Pos 0U 1192 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) 1195 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U 1196 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) 1199 #define DWT_LSUCNT_LSUCNT_Pos 0U 1200 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) 1203 #define DWT_FOLDCNT_FOLDCNT_Pos 0U 1204 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) 1207 #define DWT_MASK_MASK_Pos 0U 1208 #define DWT_MASK_MASK_Msk (0x1FUL ) 1211 #define DWT_FUNCTION_MATCHED_Pos 24U 1212 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) 1214 #define DWT_FUNCTION_DATAVADDR1_Pos 16U 1215 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) 1217 #define DWT_FUNCTION_DATAVADDR0_Pos 12U 1218 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) 1220 #define DWT_FUNCTION_DATAVSIZE_Pos 10U 1221 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) 1223 #define DWT_FUNCTION_LNK1ENA_Pos 9U 1224 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) 1226 #define DWT_FUNCTION_DATAVMATCH_Pos 8U 1227 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) 1229 #define DWT_FUNCTION_CYCMATCH_Pos 7U 1230 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) 1232 #define DWT_FUNCTION_EMITRANGE_Pos 5U 1233 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) 1235 #define DWT_FUNCTION_FUNCTION_Pos 0U 1236 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL ) 1253 __IOM uint32_t SSPSR;
1254 __IOM uint32_t CSPSR;
1255 uint32_t RESERVED0[2U];
1256 __IOM uint32_t ACPR;
1257 uint32_t RESERVED1[55U];
1258 __IOM uint32_t SPPR;
1259 uint32_t RESERVED2[131U];
1261 __IOM uint32_t FFCR;
1263 uint32_t RESERVED3[759U];
1264 __IM uint32_t TRIGGER;
1265 __IM uint32_t FIFO0;
1266 __IM uint32_t ITATBCTR2;
1267 uint32_t RESERVED4[1U];
1268 __IM uint32_t ITATBCTR0;
1269 __IM uint32_t FIFO1;
1270 __IOM uint32_t ITCTRL;
1271 uint32_t RESERVED5[39U];
1272 __IOM uint32_t CLAIMSET;
1273 __IOM uint32_t CLAIMCLR;
1274 uint32_t RESERVED7[8U];
1275 __IM uint32_t DEVID;
1276 __IM uint32_t DEVTYPE;
1280 #define TPI_ACPR_PRESCALER_Pos 0U 1281 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) 1284 #define TPI_SPPR_TXMODE_Pos 0U 1285 #define TPI_SPPR_TXMODE_Msk (0x3UL ) 1288 #define TPI_FFSR_FtNonStop_Pos 3U 1289 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) 1291 #define TPI_FFSR_TCPresent_Pos 2U 1292 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) 1294 #define TPI_FFSR_FtStopped_Pos 1U 1295 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) 1297 #define TPI_FFSR_FlInProg_Pos 0U 1298 #define TPI_FFSR_FlInProg_Msk (0x1UL ) 1301 #define TPI_FFCR_TrigIn_Pos 8U 1302 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) 1304 #define TPI_FFCR_EnFCont_Pos 1U 1305 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) 1308 #define TPI_TRIGGER_TRIGGER_Pos 0U 1309 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL ) 1312 #define TPI_FIFO0_ITM_ATVALID_Pos 29U 1313 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) 1315 #define TPI_FIFO0_ITM_bytecount_Pos 27U 1316 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) 1318 #define TPI_FIFO0_ETM_ATVALID_Pos 26U 1319 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) 1321 #define TPI_FIFO0_ETM_bytecount_Pos 24U 1322 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) 1324 #define TPI_FIFO0_ETM2_Pos 16U 1325 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) 1327 #define TPI_FIFO0_ETM1_Pos 8U 1328 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) 1330 #define TPI_FIFO0_ETM0_Pos 0U 1331 #define TPI_FIFO0_ETM0_Msk (0xFFUL ) 1334 #define TPI_ITATBCTR2_ATREADY_Pos 0U 1335 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) 1338 #define TPI_FIFO1_ITM_ATVALID_Pos 29U 1339 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) 1341 #define TPI_FIFO1_ITM_bytecount_Pos 27U 1342 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) 1344 #define TPI_FIFO1_ETM_ATVALID_Pos 26U 1345 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) 1347 #define TPI_FIFO1_ETM_bytecount_Pos 24U 1348 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) 1350 #define TPI_FIFO1_ITM2_Pos 16U 1351 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) 1353 #define TPI_FIFO1_ITM1_Pos 8U 1354 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) 1356 #define TPI_FIFO1_ITM0_Pos 0U 1357 #define TPI_FIFO1_ITM0_Msk (0xFFUL ) 1360 #define TPI_ITATBCTR0_ATREADY_Pos 0U 1361 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) 1364 #define TPI_ITCTRL_Mode_Pos 0U 1365 #define TPI_ITCTRL_Mode_Msk (0x1UL ) 1368 #define TPI_DEVID_NRZVALID_Pos 11U 1369 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) 1371 #define TPI_DEVID_MANCVALID_Pos 10U 1372 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) 1374 #define TPI_DEVID_PTINVALID_Pos 9U 1375 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) 1377 #define TPI_DEVID_MinBufSz_Pos 6U 1378 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) 1380 #define TPI_DEVID_AsynClkIn_Pos 5U 1381 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) 1383 #define TPI_DEVID_NrTraceInput_Pos 0U 1384 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL ) 1387 #define TPI_DEVTYPE_MajorType_Pos 4U 1388 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) 1390 #define TPI_DEVTYPE_SubType_Pos 0U 1391 #define TPI_DEVTYPE_SubType_Msk (0xFUL ) 1396 #if (__MPU_PRESENT == 1U) 1410 __IOM uint32_t CTRL;
1412 __IOM uint32_t RBAR;
1413 __IOM uint32_t RASR;
1414 __IOM uint32_t RBAR_A1;
1415 __IOM uint32_t RASR_A1;
1416 __IOM uint32_t RBAR_A2;
1417 __IOM uint32_t RASR_A2;
1418 __IOM uint32_t RBAR_A3;
1419 __IOM uint32_t RASR_A3;
1423 #define MPU_TYPE_IREGION_Pos 16U 1424 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 1426 #define MPU_TYPE_DREGION_Pos 8U 1427 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 1429 #define MPU_TYPE_SEPARATE_Pos 0U 1430 #define MPU_TYPE_SEPARATE_Msk (1UL ) 1433 #define MPU_CTRL_PRIVDEFENA_Pos 2U 1434 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 1436 #define MPU_CTRL_HFNMIENA_Pos 1U 1437 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 1439 #define MPU_CTRL_ENABLE_Pos 0U 1440 #define MPU_CTRL_ENABLE_Msk (1UL ) 1443 #define MPU_RNR_REGION_Pos 0U 1444 #define MPU_RNR_REGION_Msk (0xFFUL ) 1447 #define MPU_RBAR_ADDR_Pos 5U 1448 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) 1450 #define MPU_RBAR_VALID_Pos 4U 1451 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 1453 #define MPU_RBAR_REGION_Pos 0U 1454 #define MPU_RBAR_REGION_Msk (0xFUL ) 1457 #define MPU_RASR_ATTRS_Pos 16U 1458 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 1460 #define MPU_RASR_XN_Pos 28U 1461 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) 1463 #define MPU_RASR_AP_Pos 24U 1464 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) 1466 #define MPU_RASR_TEX_Pos 19U 1467 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) 1469 #define MPU_RASR_S_Pos 18U 1470 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) 1472 #define MPU_RASR_C_Pos 17U 1473 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) 1475 #define MPU_RASR_B_Pos 16U 1476 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) 1478 #define MPU_RASR_SRD_Pos 8U 1479 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 1481 #define MPU_RASR_SIZE_Pos 1U 1482 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 1484 #define MPU_RASR_ENABLE_Pos 0U 1485 #define MPU_RASR_ENABLE_Msk (1UL ) 1491 #if (__FPU_PRESENT == 1U) 1504 uint32_t RESERVED0[1U];
1505 __IOM uint32_t FPCCR;
1506 __IOM uint32_t FPCAR;
1507 __IOM uint32_t FPDSCR;
1508 __IM uint32_t MVFR0;
1509 __IM uint32_t MVFR1;
1510 __IM uint32_t MVFR2;
1514 #define FPU_FPCCR_ASPEN_Pos 31U 1515 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) 1517 #define FPU_FPCCR_LSPEN_Pos 30U 1518 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) 1520 #define FPU_FPCCR_MONRDY_Pos 8U 1521 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) 1523 #define FPU_FPCCR_BFRDY_Pos 6U 1524 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) 1526 #define FPU_FPCCR_MMRDY_Pos 5U 1527 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) 1529 #define FPU_FPCCR_HFRDY_Pos 4U 1530 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) 1532 #define FPU_FPCCR_THREAD_Pos 3U 1533 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) 1535 #define FPU_FPCCR_USER_Pos 1U 1536 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) 1538 #define FPU_FPCCR_LSPACT_Pos 0U 1539 #define FPU_FPCCR_LSPACT_Msk (1UL ) 1542 #define FPU_FPCAR_ADDRESS_Pos 3U 1543 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) 1546 #define FPU_FPDSCR_AHP_Pos 26U 1547 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) 1549 #define FPU_FPDSCR_DN_Pos 25U 1550 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) 1552 #define FPU_FPDSCR_FZ_Pos 24U 1553 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) 1555 #define FPU_FPDSCR_RMode_Pos 22U 1556 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) 1559 #define FPU_MVFR0_FP_rounding_modes_Pos 28U 1560 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) 1562 #define FPU_MVFR0_Short_vectors_Pos 24U 1563 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) 1565 #define FPU_MVFR0_Square_root_Pos 20U 1566 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) 1568 #define FPU_MVFR0_Divide_Pos 16U 1569 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) 1571 #define FPU_MVFR0_FP_excep_trapping_Pos 12U 1572 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) 1574 #define FPU_MVFR0_Double_precision_Pos 8U 1575 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) 1577 #define FPU_MVFR0_Single_precision_Pos 4U 1578 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) 1580 #define FPU_MVFR0_A_SIMD_registers_Pos 0U 1581 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) 1584 #define FPU_MVFR1_FP_fused_MAC_Pos 28U 1585 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) 1587 #define FPU_MVFR1_FP_HPFP_Pos 24U 1588 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) 1590 #define FPU_MVFR1_D_NaN_mode_Pos 4U 1591 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) 1593 #define FPU_MVFR1_FtZ_mode_Pos 0U 1594 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL ) 1614 __IOM uint32_t DHCSR;
1615 __OM uint32_t DCRSR;
1616 __IOM uint32_t DCRDR;
1617 __IOM uint32_t DEMCR;
1621 #define CoreDebug_DHCSR_DBGKEY_Pos 16U 1622 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) 1624 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U 1625 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) 1627 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U 1628 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) 1630 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U 1631 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) 1633 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U 1634 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) 1636 #define CoreDebug_DHCSR_S_HALT_Pos 17U 1637 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) 1639 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U 1640 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) 1642 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U 1643 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) 1645 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U 1646 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) 1648 #define CoreDebug_DHCSR_C_STEP_Pos 2U 1649 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) 1651 #define CoreDebug_DHCSR_C_HALT_Pos 1U 1652 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) 1654 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U 1655 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) 1658 #define CoreDebug_DCRSR_REGWnR_Pos 16U 1659 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) 1661 #define CoreDebug_DCRSR_REGSEL_Pos 0U 1662 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) 1665 #define CoreDebug_DEMCR_TRCENA_Pos 24U 1666 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) 1668 #define CoreDebug_DEMCR_MON_REQ_Pos 19U 1669 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) 1671 #define CoreDebug_DEMCR_MON_STEP_Pos 18U 1672 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) 1674 #define CoreDebug_DEMCR_MON_PEND_Pos 17U 1675 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) 1677 #define CoreDebug_DEMCR_MON_EN_Pos 16U 1678 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) 1680 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U 1681 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) 1683 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U 1684 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) 1686 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U 1687 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) 1689 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U 1690 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) 1692 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U 1693 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) 1695 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U 1696 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) 1698 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U 1699 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) 1701 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U 1702 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) 1720 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) 1728 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) 1741 #define SCS_BASE (0xE000E000UL) 1742 #define ITM_BASE (0xE0000000UL) 1743 #define DWT_BASE (0xE0001000UL) 1744 #define TPI_BASE (0xE0040000UL) 1745 #define CoreDebug_BASE (0xE000EDF0UL) 1746 #define SysTick_BASE (SCS_BASE + 0x0010UL) 1747 #define NVIC_BASE (SCS_BASE + 0x0100UL) 1748 #define SCB_BASE (SCS_BASE + 0x0D00UL) 1750 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 1751 #define SCB ((SCB_Type *) SCB_BASE ) 1752 #define SysTick ((SysTick_Type *) SysTick_BASE ) 1753 #define NVIC ((NVIC_Type *) NVIC_BASE ) 1754 #define ITM ((ITM_Type *) ITM_BASE ) 1755 #define DWT ((DWT_Type *) DWT_BASE ) 1756 #define TPI ((TPI_Type *) TPI_BASE ) 1757 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) 1759 #if (__MPU_PRESENT == 1U) 1760 #define MPU_BASE (SCS_BASE + 0x0D90UL) 1761 #define MPU ((MPU_Type *) MPU_BASE ) 1764 #if (__FPU_PRESENT == 1U) 1765 #define FPU_BASE (SCS_BASE + 0x0F30UL) 1766 #define FPU ((FPU_Type *) FPU_BASE ) 1807 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1809 reg_value =
SCB->AIRCR;
1811 reg_value = (reg_value |
1813 (PriorityGroupTmp << 8U) );
1814 SCB->AIRCR = reg_value;
1838 return((uint32_t)(((
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1849 NVIC->ISER[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1860 NVIC->ICER[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1873 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1884 NVIC->ISPR[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1895 NVIC->ICPR[(((uint32_t)(int32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1908 return((uint32_t)(((
NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1921 if ((int32_t)(IRQn) < 0)
1923 SCB->SHPR[(((uint32_t)(int32_t)
IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1944 if ((int32_t)(IRQn) < 0)
1946 return(((uint32_t)
SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U -
__NVIC_PRIO_BITS)));
1966 __STATIC_INLINE uint32_t
NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1968 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1969 uint32_t PreemptPriorityBits;
1970 uint32_t SubPriorityBits;
1973 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1976 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1977 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1993 __STATIC_INLINE
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t*
const pPreemptPriority, uint32_t*
const pSubPriority)
1995 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1996 uint32_t PreemptPriorityBits;
1997 uint32_t SubPriorityBits;
2000 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
2002 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2003 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2050 if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
2054 else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
2078 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 2079 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 2088 #if (__ICACHE_PRESENT == 1U) 2105 #if (__ICACHE_PRESENT == 1U) 2122 #if (__ICACHE_PRESENT == 1U) 2138 #if (__DCACHE_PRESENT == 1U) 2143 SCB->CSSELR = (0U << 1U) | 0U;
2146 ccsidr =
SCB->CCSIDR;
2149 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2151 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2155 #if defined ( __CC_ARM ) 2156 __schedule_barrier();
2176 #if (__DCACHE_PRESENT == 1U) 2181 SCB->CSSELR = (0U << 1U) | 0U;
2184 ccsidr =
SCB->CCSIDR;
2189 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2191 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2195 #if defined ( __CC_ARM ) 2196 __schedule_barrier();
2213 #if (__DCACHE_PRESENT == 1U) 2218 SCB->CSSELR = (0U << 1U) | 0U;
2221 ccsidr =
SCB->CCSIDR;
2224 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2226 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2230 #if defined ( __CC_ARM ) 2231 __schedule_barrier();
2248 #if (__DCACHE_PRESENT == 1U) 2253 SCB->CSSELR = (0U << 1U) | 0U;
2256 ccsidr =
SCB->CCSIDR;
2259 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2261 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2265 #if defined ( __CC_ARM ) 2266 __schedule_barrier();
2283 #if (__DCACHE_PRESENT == 1U) 2288 SCB->CSSELR = (0U << 1U) | 0U;
2291 ccsidr =
SCB->CCSIDR;
2294 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2296 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2300 #if defined ( __CC_ARM ) 2301 __schedule_barrier();
2320 #if (__DCACHE_PRESENT == 1U) 2321 int32_t op_size = dsize;
2322 uint32_t op_addr = (uint32_t)addr;
2323 int32_t linesize = 32U;
2327 while (op_size > 0) {
2328 SCB->DCIMVAC = op_addr;
2329 op_addr += linesize;
2330 op_size -= linesize;
2347 #if (__DCACHE_PRESENT == 1) 2348 int32_t op_size = dsize;
2349 uint32_t op_addr = (uint32_t) addr;
2350 int32_t linesize = 32U;
2354 while (op_size > 0) {
2355 SCB->DCCMVAC = op_addr;
2356 op_addr += linesize;
2357 op_size -= linesize;
2374 #if (__DCACHE_PRESENT == 1U) 2375 int32_t op_size = dsize;
2376 uint32_t op_addr = (uint32_t) addr;
2377 int32_t linesize = 32U;
2381 while (op_size > 0) {
2382 SCB->DCCIMVAC = op_addr;
2383 op_addr += linesize;
2384 op_size -= linesize;
2405 #if (__Vendor_SysTickConfig == 0U) 2425 SysTick->LOAD = (uint32_t)(ticks - 1UL);
2449 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U 2463 ((
ITM->TER & 1UL ) != 0UL) )
2465 while (
ITM->PORT[0U].u32 == 0UL)
2469 ITM->PORT[0U].u8 = (uint8_t)ch;
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
#define SCB_DCCSW_WAY_Msk
#define SCB_DCCISW_SET_Msk
CMSIS Cortex-M Core Function Access Header File.
__STATIC_INLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
static uip_ds6_addr_t * addr
Pointer to a nbr cache entry.
__STATIC_INLINE void SCB_DisableDCache(void)
Disable D-Cache.
#define SCB_AIRCR_VECTKEY_Pos
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
#define SysTick_CTRL_CLKSOURCE_Msk
Structure type to access the System Control Block (SCB).
Structure type to access the Data Watchpoint and Trace Register (DWT).
CMSIS Cortex-M Core Instruction Access Header File.
__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean by address.
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
#define SCB_DCCISW_WAY_Msk
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
#define ITM_RXBUFFER_EMPTY
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
#define SCB_DCCISW_WAY_Pos
__STATIC_INLINE void SCB_EnableDCache(void)
Enable D-Cache.
__STATIC_INLINE void SCB_DisableICache(void)
Disable I-Cache.
volatile int32_t ITM_RxBuffer
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
__STATIC_INLINE void SCB_EnableICache(void)
Enable I-Cache.
__STATIC_INLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
#define SysTick_CTRL_TICKINT_Msk
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Structure type to access the System Timer (SysTick).
#define SCB_DCCSW_SET_Pos
Structure type to access the Core Debug Register (CoreDebug).
#define SCB_DCISW_WAY_Msk
CMSIS Cortex-M SIMD Header File.
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Union type to access the Application Program Status Register (APSR).
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
#define SCB_AIRCR_VECTKEY_Msk
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn)
Get External Interrupt Enable State.
__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
#define SCB_DCCSW_SET_Msk
__STATIC_INLINE void __NOP(void)
No Operation.
#define SCB_AIRCR_PRIGROUP_Msk
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
#define SCB_DCISW_WAY_Pos
#define SCB_DCISW_SET_Pos
Union type to access the Control Registers (CONTROL).
Structure type to access the Trace Port Interface Register (TPI).
#define SysTick_LOAD_RELOAD_Msk
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
__STATIC_INLINE void __DSB(void)
Data Synchronization Barrier.
Union type to access the Interrupt Program Status Register (IPSR).
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Union type to access the Special-Purpose Program Status Registers (xPSR).
__STATIC_INLINE void __ISB(void)
Instruction Synchronization Barrier.
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
#define SCB_DCCSW_WAY_Pos
#define SysTick_CTRL_ENABLE_Msk
__STATIC_INLINE void SCB_CleanDCache(void)
Clean D-Cache.
#define SCB_DCCISW_SET_Pos
#define SCB_DCISW_SET_Msk
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
#define __NVIC_PRIO_BITS
Number of Bits used for Priority Levels.
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
#define ITM_TCR_ITMENA_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Invalidate by address.
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
#define SCB_AIRCR_PRIGROUP_Pos