35 #ifndef __CMSIS_ARMCC_H 36 #define __CMSIS_ARMCC_H 39 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) 40 #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 59 register uint32_t __regControl __ASM(
"control");
71 register uint32_t __regControl __ASM(
"control");
72 __regControl = control;
83 register uint32_t __regIPSR __ASM(
"ipsr");
95 register uint32_t __regAPSR __ASM(
"apsr");
107 register uint32_t __regXPSR __ASM(
"xpsr");
119 register uint32_t __regProcessStackPointer __ASM(
"psp");
120 return(__regProcessStackPointer);
131 register uint32_t __regProcessStackPointer __ASM(
"psp");
132 __regProcessStackPointer = topOfProcStack;
143 register uint32_t __regMainStackPointer __ASM(
"msp");
144 return(__regMainStackPointer);
155 register uint32_t __regMainStackPointer __ASM(
"msp");
156 __regMainStackPointer = topOfMainStack;
167 register uint32_t __regPriMask __ASM(
"primask");
168 return(__regPriMask);
179 register uint32_t __regPriMask __ASM(
"primask");
180 __regPriMask = (priMask);
184 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) 191 #define __enable_fault_irq __enable_fiq 199 #define __disable_fault_irq __disable_fiq 207 __STATIC_INLINE uint32_t __get_BASEPRI(
void)
209 register uint32_t __regBasePri __ASM(
"basepri");
210 return(__regBasePri);
219 __STATIC_INLINE
void __set_BASEPRI(uint32_t basePri)
221 register uint32_t __regBasePri __ASM(
"basepri");
222 __regBasePri = (basePri & 0xFFU);
232 __STATIC_INLINE
void __set_BASEPRI_MAX(uint32_t basePri)
234 register uint32_t __regBasePriMax __ASM(
"basepri_max");
235 __regBasePriMax = (basePri & 0xFFU);
244 __STATIC_INLINE uint32_t __get_FAULTMASK(
void)
246 register uint32_t __regFaultMask __ASM(
"faultmask");
247 return(__regFaultMask);
256 __STATIC_INLINE
void __set_FAULTMASK(uint32_t faultMask)
258 register uint32_t __regFaultMask __ASM(
"faultmask");
259 __regFaultMask = (faultMask & (uint32_t)1);
265 #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) 272 __STATIC_INLINE uint32_t __get_FPSCR(
void)
274 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) 275 register uint32_t __regfpscr __ASM(
"fpscr");
288 __STATIC_INLINE
void __set_FPSCR(uint32_t fpscr)
290 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) 291 register uint32_t __regfpscr __ASM(
"fpscr");
292 __regfpscr = (fpscr);
344 #define __ISB() do {\ 345 __schedule_barrier();\ 347 __schedule_barrier();\ 355 #define __DSB() do {\ 356 __schedule_barrier();\ 358 __schedule_barrier();\ 366 #define __DMB() do {\ 367 __schedule_barrier();\ 369 __schedule_barrier();\ 387 #ifndef __NO_EMBEDDED_ASM 388 __attribute__((section(
".rev16_text"))) __STATIC_INLINE __ASM uint32_t
__REV16(uint32_t value)
401 #ifndef __NO_EMBEDDED_ASM 402 __attribute__((section(
".revsh_text"))) __STATIC_INLINE __ASM int32_t
__REVSH(int32_t value)
427 #define __BKPT(value) __breakpoint(value) 436 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) 437 #define __RBIT __rbit 439 __attribute__((always_inline)) __STATIC_INLINE uint32_t
__RBIT(uint32_t value)
442 int32_t s = 4 * 8 - 1;
445 for (value >>= 1U; value; value >>= 1U)
448 result |= value & 1U;
466 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) 474 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 475 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) 477 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") 487 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 488 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) 490 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") 500 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 501 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) 503 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") 515 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 516 #define __STREXB(value, ptr) __strex(value, ptr) 518 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 530 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 531 #define __STREXH(value, ptr) __strex(value, ptr) 533 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 545 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 546 #define __STREXW(value, ptr) __strex(value, ptr) 548 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 556 #define __CLREX __clrex 566 #define __SSAT __ssat 576 #define __USAT __usat 586 #ifndef __NO_EMBEDDED_ASM 587 __attribute__((section(
".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
601 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) 610 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) 619 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) 628 #define __STRBT(value, ptr) __strt(value, ptr) 637 #define __STRHT(value, ptr) __strt(value, ptr) 646 #define __STRT(value, ptr) __strt(value, ptr) 659 #if (__CORTEX_M >= 0x04U) 661 #define __SADD8 __sadd8 662 #define __QADD8 __qadd8 663 #define __SHADD8 __shadd8 664 #define __UADD8 __uadd8 665 #define __UQADD8 __uqadd8 666 #define __UHADD8 __uhadd8 667 #define __SSUB8 __ssub8 668 #define __QSUB8 __qsub8 669 #define __SHSUB8 __shsub8 670 #define __USUB8 __usub8 671 #define __UQSUB8 __uqsub8 672 #define __UHSUB8 __uhsub8 673 #define __SADD16 __sadd16 674 #define __QADD16 __qadd16 675 #define __SHADD16 __shadd16 676 #define __UADD16 __uadd16 677 #define __UQADD16 __uqadd16 678 #define __UHADD16 __uhadd16 679 #define __SSUB16 __ssub16 680 #define __QSUB16 __qsub16 681 #define __SHSUB16 __shsub16 682 #define __USUB16 __usub16 683 #define __UQSUB16 __uqsub16 684 #define __UHSUB16 __uhsub16 685 #define __SASX __sasx 686 #define __QASX __qasx 687 #define __SHASX __shasx 688 #define __UASX __uasx 689 #define __UQASX __uqasx 690 #define __UHASX __uhasx 691 #define __SSAX __ssax 692 #define __QSAX __qsax 693 #define __SHSAX __shsax 694 #define __USAX __usax 695 #define __UQSAX __uqsax 696 #define __UHSAX __uhsax 697 #define __USAD8 __usad8 698 #define __USADA8 __usada8 699 #define __SSAT16 __ssat16 700 #define __USAT16 __usat16 701 #define __UXTB16 __uxtb16 702 #define __UXTAB16 __uxtab16 703 #define __SXTB16 __sxtb16 704 #define __SXTAB16 __sxtab16 705 #define __SMUAD __smuad 706 #define __SMUADX __smuadx 707 #define __SMLAD __smlad 708 #define __SMLADX __smladx 709 #define __SMLALD __smlald 710 #define __SMLALDX __smlaldx 711 #define __SMUSD __smusd 712 #define __SMUSDX __smusdx 713 #define __SMLSD __smlsd 714 #define __SMLSDX __smlsdx 715 #define __SMLSLD __smlsld 716 #define __SMLSLDX __smlsldx 718 #define __QADD __qadd 719 #define __QSUB __qsub 721 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ 722 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 724 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ 725 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 727 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ 728 ((int64_t)(ARG3) << 32U) ) >> 32U)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
__STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
Reverse byte order in signed short value.
__STATIC_INLINE uint32_t __get_xPSR(void)
Get xPSR Register.
__STATIC_INLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
__STATIC_INLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
__STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
Reverse byte order (16 bit)
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
__STATIC_INLINE uint32_t __get_CONTROL(void)
Get Control Register.
__STATIC_INLINE uint32_t __get_IPSR(void)
Get IPSR Register.
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
__STATIC_INLINE uint32_t __RBIT(uint32_t value)
Reverse bit order of value.
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
__STATIC_INLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.