52 #define SYS_CTRL_32MHZ 32000000 53 #define SYS_CTRL_16MHZ 16000000 54 #define SYS_CTRL_8MHZ 8000000 55 #define SYS_CTRL_4MHZ 4000000 56 #define SYS_CTRL_2MHZ 2000000 57 #define SYS_CTRL_1MHZ 1000000 58 #define SYS_CTRL_500KHZ 500000 59 #define SYS_CTRL_250KHZ 250000 65 #define SYS_CTRL_CLOCK_CTRL 0x400D2000 66 #define SYS_CTRL_CLOCK_STA 0x400D2004 67 #define SYS_CTRL_RCGCGPT 0x400D2008 68 #define SYS_CTRL_SCGCGPT 0x400D200C 69 #define SYS_CTRL_DCGCGPT 0x400D2010 70 #define SYS_CTRL_SRGPT 0x400D2014 71 #define SYS_CTRL_RCGCSSI 0x400D2018 72 #define SYS_CTRL_SCGCSSI 0x400D201C 73 #define SYS_CTRL_DCGCSSI 0x400D2020 74 #define SYS_CTRL_SRSSI 0x400D2024 75 #define SYS_CTRL_RCGCUART 0x400D2028 76 #define SYS_CTRL_SCGCUART 0x400D202C 77 #define SYS_CTRL_DCGCUART 0x400D2030 78 #define SYS_CTRL_SRUART 0x400D2034 79 #define SYS_CTRL_RCGCI2C 0x400D2038 80 #define SYS_CTRL_SCGCI2C 0x400D203C 81 #define SYS_CTRL_DCGCI2C 0x400D2040 82 #define SYS_CTRL_SRI2C 0x400D2044 83 #define SYS_CTRL_RCGCSEC 0x400D2048 84 #define SYS_CTRL_SCGCSEC 0x400D204C 85 #define SYS_CTRL_DCGCSEC 0x400D2050 86 #define SYS_CTRL_SRSEC 0x400D2054 87 #define SYS_CTRL_PMCTL 0x400D2058 88 #define SYS_CTRL_SRCRC 0x400D205C 89 #define SYS_CTRL_PWRDBG 0x400D2074 90 #define SYS_CTRL_CLD 0x400D2080 91 #define SYS_CTRL_IWE 0x400D2094 92 #define SYS_CTRL_I_MAP 0x400D2098 93 #define SYS_CTRL_RCGCRFC 0x400D20A8 94 #define SYS_CTRL_SCGCRFC 0x400D20AC 95 #define SYS_CTRL_DCGCRFC 0x400D20B0 96 #define SYS_CTRL_EMUOVR 0x400D20B4 102 #define SYS_CTRL_CLOCK_CTRL_OSC32K_CALDIS 0x02000000 103 #define SYS_CTRL_CLOCK_CTRL_OSC32K 0x01000000 104 #define SYS_CTRL_CLOCK_CTRL_AMP_DET 0x00200000 105 #define SYS_CTRL_CLOCK_CTRL_OSC_PD 0x00020000 106 #define SYS_CTRL_CLOCK_CTRL_OSC 0x00010000 107 #define SYS_CTRL_CLOCK_CTRL_IO_DIV 0x00000700 108 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV 0x00000007 114 #define SYS_CTRL_CLOCK_STA_SYNC_32K 0x04000000 115 #define SYS_CTRL_CLOCK_STA_OSC32K_CALDIS 0x02000000 116 #define SYS_CTRL_CLOCK_STA_OSC32K 0x01000000 117 #define SYS_CTRL_CLOCK_STA_RST 0x00C00000 118 #define SYS_CTRL_CLOCK_STA_RST_S 22 119 #define SYS_CTRL_CLOCK_STA_RST_POR 0 120 #define SYS_CTRL_CLOCK_STA_RST_EXT 1 121 #define SYS_CTRL_CLOCK_STA_RST_WDT 2 122 #define SYS_CTRL_CLOCK_STA_RST_CLD_SW 3 123 #define SYS_CTRL_CLOCK_STA_SOURCE_CHANGE 0x00100000 124 #define SYS_CTRL_CLOCK_STA_XOSC_STB 0x00080000 125 #define SYS_CTRL_CLOCK_STA_HSOSC_STB 0x00040000 126 #define SYS_CTRL_CLOCK_STA_OSC_PD 0x00020000 127 #define SYS_CTRL_CLOCK_STA_OSC 0x00010000 128 #define SYS_CTRL_CLOCK_STA_IO_DIV 0x00000700 129 #define SYS_CTRL_CLOCK_STA_RTCLK_FREQ 0x00000018 130 #define SYS_CTRL_CLOCK_STA_SYS_DIV 0x00000007 136 #define SYS_CTRL_RCGCGPT_GPT3 0x00000008 137 #define SYS_CTRL_RCGCGPT_GPT2 0x00000004 138 #define SYS_CTRL_RCGCGPT_GPT1 0x00000002 139 #define SYS_CTRL_RCGCGPT_GPT0 0x00000001 145 #define SYS_CTRL_SCGCGPT_GPT3 0x00000008 146 #define SYS_CTRL_SCGCGPT_GPT2 0x00000004 147 #define SYS_CTRL_SCGCGPT_GPT1 0x00000002 148 #define SYS_CTRL_SCGCGPT_GPT0 0x00000001 154 #define SYS_CTRL_DCGCGPT_GPT3 0x00000008 155 #define SYS_CTRL_DCGCGPT_GPT2 0x00000004 156 #define SYS_CTRL_DCGCGPT_GPT1 0x00000002 157 #define SYS_CTRL_DCGCGPT_GPT0 0x00000001 163 #define SYS_CTRL_SRGPT_GPT3 0x00000008 164 #define SYS_CTRL_SRGPT_GPT2 0x00000004 165 #define SYS_CTRL_SRGPT_GPT1 0x00000002 166 #define SYS_CTRL_SRGPT_GPT0 0x00000001 172 #define SYS_CTRL_RCGCSEC_AES 0x00000002 173 #define SYS_CTRL_RCGCSEC_PKA 0x00000001 179 #define SYS_CTRL_SCGCSEC_AES 0x00000002 180 #define SYS_CTRL_SCGCSEC_PKA 0x00000001 186 #define SYS_CTRL_DCGCSEC_AES 0x00000002 187 #define SYS_CTRL_DCGCSEC_PKA 0x00000001 193 #define SYS_CTRL_SRSEC_AES 0x00000002 194 #define SYS_CTRL_SRSEC_PKA 0x00000001 200 #define SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008 206 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_32MHZ 0x00000000 207 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ 0x00000001 208 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_8MHZ 0x00000002 209 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_4MHZ 0x00000003 210 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_2MHZ 0x00000004 211 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_1MHZ 0x00000005 212 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_500KHZ 0x00000006 213 #define SYS_CTRL_CLOCK_CTRL_SYS_DIV_250KHZ 0x00000007 219 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_32MHZ 0x00000000 220 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ 0x00000100 221 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_8MHZ 0x00000200 222 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_4MHZ 0x00000300 223 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_2MHZ 0x00000400 224 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_1MHZ 0x00000500 225 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_500KHZ 0x00000600 226 #define SYS_CTRL_CLOCK_CTRL_IO_DIV_250KHZ 0x00000700 232 #define SYS_CTRL_RCGCUART_UART1 0x00000002 233 #define SYS_CTRL_RCGCUART_UART0 0x00000001 239 #define SYS_CTRL_SCGCUART_UART1 0x00000002 240 #define SYS_CTRL_SCGCUART_UART0 0x00000001 246 #define SYS_CTRL_DCGCUART_UART1 0x00000002 247 #define SYS_CTRL_DCGCUART_UART0 0x00000001 253 #define SYS_CTRL_SRUART_UART1 0x00000002 254 #define SYS_CTRL_SRUART_UART0 0x00000001 260 #define SYS_CTRL_PMCTL_PM3 0x00000003 261 #define SYS_CTRL_PMCTL_PM2 0x00000002 262 #define SYS_CTRL_PMCTL_PM1 0x00000001 263 #define SYS_CTRL_PMCTL_PM0 0x00000000 273 #ifdef SYS_CTRL_CONF_OSC32K_USE_XTAL 274 #define SYS_CTRL_OSC32K_USE_XTAL SYS_CTRL_CONF_OSC32K_USE_XTAL 276 #define SYS_CTRL_OSC32K_USE_XTAL 0 283 #ifdef SYS_CTRL_CONF_SYS_DIV 284 #if SYS_CTRL_CONF_SYS_DIV & ~SYS_CTRL_CLOCK_CTRL_SYS_DIV 285 #error Invalid system clock divisor 287 #define SYS_CTRL_SYS_DIV SYS_CTRL_CONF_SYS_DIV 289 #define SYS_CTRL_SYS_DIV SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ 292 #ifdef SYS_CTRL_CONF_IO_DIV 293 #if SYS_CTRL_CONF_IO_DIV & ~SYS_CTRL_CLOCK_CTRL_IO_DIV 294 #error Invalid I/O clock divisor 296 #define SYS_CTRL_IO_DIV SYS_CTRL_CONF_IO_DIV 298 #define SYS_CTRL_IO_DIV SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ 302 #define SYS_CTRL_SYS_CLOCK (SYS_CTRL_32MHZ >> SYS_CTRL_SYS_DIV) 304 #define SYS_CTRL_IO_CLOCK (SYS_CTRL_32MHZ >> (SYS_CTRL_IO_DIV >> 8)) const char * sys_ctrl_get_reset_cause_str(void)
Gets a string describing the cause of the last reset.
uint32_t sys_ctrl_get_io_clock(void)
Returns the actual io clock in Hz.
int sys_ctrl_get_reset_cause(void)
Gets the cause of the last reset.
uint32_t sys_ctrl_get_sys_clock(void)
Returns the actual system clock in Hz.
void sys_ctrl_init()
Initialises the System Control Driver.
void sys_ctrl_reset()
Generates a warm reset through the SYS_CTRL_PWRDBG register.