Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

#include <arch/cpu/arm/cortex-m/CMSIS/core_cm0.h>

Data Fields
__IOM uint32_t	ISER [1U]

__IOM uint32_t	ICER [1U]

__IOM uint32_t	ISPR [1U]

__IOM uint32_t	ICPR [1U]

__IOM uint32_t	IP [8U]

__IOM uint32_t	IABR [8U]

__IOM uint8_t	IP [240U]

__OM uint32_t	STIR

Detailed Description

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Definition at line 362 of file core_cm0.h.

Field Documentation

◆ IABR

__IOM uint32_t NVIC_Type::IABR

Offset: 0x200 (R/W) Interrupt Active bit Register

Definition at line 393 of file core_cm3.h.

◆ ICER

__IOM uint32_t NVIC_Type::ICER

Offset: 0x080 (R/W) Interrupt Clear Enable Register

Definition at line 366 of file core_cm0.h.

◆ ICPR

__IOM uint32_t NVIC_Type::ICPR

Offset: 0x180 (R/W) Interrupt Clear Pending Register

Definition at line 370 of file core_cm0.h.

◆ IP [1/2]

__IOM uint8_t NVIC_Type::IP

Offset: 0x300 (R/W) Interrupt Priority Register

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 373 of file core_cm0.h.

◆ IP [2/2]

__IOM uint8_t NVIC_Type::IP[240U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 395 of file core_cm3.h.

◆ ISER

__IOM uint32_t NVIC_Type::ISER

Offset: 0x000 (R/W) Interrupt Set Enable Register

Definition at line 364 of file core_cm0.h.

◆ ISPR

__IOM uint32_t NVIC_Type::ISPR

Offset: 0x100 (R/W) Interrupt Set Pending Register

Definition at line 368 of file core_cm0.h.

◆ STIR

__OM uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

Definition at line 397 of file core_cm3.h.

Data Fields