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smwdthrosc.h
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1 /*
2  * Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \addtogroup cc2538
33  * @{
34  *
35  * \defgroup cc2538-smwdthrosc cc2538 Sleep Timer and Watchdog
36  *
37  * Register declarations for the cc2538 Sleep Timer and Watchdog
38  * @{
39  *
40  * \file
41  * Header file with register declarations and bit masks for the cc2538
42  * Sleep Timer and Watchdog
43  */
44 #ifndef SMWDTHROSC_H_
45 #define SMWDTHROSC_H_
46 /*---------------------------------------------------------------------------*/
47 /** \name ST and WDT Register offset declarations
48  * @{
49  */
50 #define SMWDTHROSC_WDCTL 0x400D5000 /**< Watchdog Control */
51 #define SMWDTHROSC_ST0 0x400D5040 /**< ST count/compare value 0 */
52 #define SMWDTHROSC_ST1 0x400D5044 /**< ST count/compare value 1 */
53 #define SMWDTHROSC_ST2 0x400D5048 /**< ST count/compare value 2 */
54 #define SMWDTHROSC_ST3 0x400D504C /**< ST count/compare value 3 */
55 #define SMWDTHROSC_STLOAD 0x400D5050 /**< Compare value load status */
56 #define SMWDTHROSC_STCC 0x400D5054 /**< ST capture control */
57 #define SMWDTHROSC_STCS 0x400D5058 /**< ST capture status */
58 #define SMWDTHROSC_STCV0 0x400D505C /**< ST capture value 0 */
59 #define SMWDTHROSC_STCV1 0x400D5060 /**< ST capture value 1 */
60 #define SMWDTHROSC_STCV2 0x400D5064 /**< ST capture value 2 */
61 #define SMWDTHROSC_STCV3 0x400D5068 /**< ST capture value 3 */
62 /** @} */
63 /*---------------------------------------------------------------------------*/
64 /** \name SMWDTHROSC_WDCTL register bit masks
65  * @{
66  */
67 #define SMWDTHROSC_WDCTL_CLR 0x000000F0 /**< Clear timer mask */
68 #define SMWDTHROSC_WDCTL_CLR_3 0x00000080 /**< Clear timer mask[3] */
69 #define SMWDTHROSC_WDCTL_CLR_2 0x00000040 /**< Clear timer mask[2] */
70 #define SMWDTHROSC_WDCTL_CLR_1 0x00000020 /**< Clear timer mask[1] */
71 #define SMWDTHROSC_WDCTL_CLR_0 0x00000010 /**< Clear timer mask[0] */
72 #define SMWDTHROSC_WDCTL_EN 0x00000008 /**< Enable mask */
73 #define SMWDTHROSC_WDCTL_MODE 0x00000004 /**< Mode select mask */
74 #define SMWDTHROSC_WDCTL_INT 0x00000003 /**< Interval Select mask */
75 /** @} */
76 /*---------------------------------------------------------------------------*/
77 /** \name SMWDTHROSC_ST[0:3] register bit masks
78  * @{
79  */
80 #define SMWDTHROSC_ST0_ST0 0x000000FF /**< ST count/compare bits [7:0] */
81 #define SMWDTHROSC_ST1_ST1 0x000000FF /**< ST count/compare bits [15:8] */
82 #define SMWDTHROSC_ST2_ST2 0x000000FF /**< ST count/compare bits [23:16] */
83 #define SMWDTHROSC_ST3_ST3 0x000000FF /**< ST count/compare bits [31:24] */
84 /** @} */
85 /*---------------------------------------------------------------------------*/
86 /** \name SMWDTHROSC_STLOAD register bit masks
87  * @{
88  */
89 #define SMWDTHROSC_STLOAD_STLOAD 0x00000001 /**< STx upload status signal */
90 /** @} */
91 /*---------------------------------------------------------------------------*/
92 /** \name SMWDTHROSC_STCC register bit masks
93  * @{
94  */
95 #define SMWDTHROSC_STCC_PORT 0x00000038 /**< Port select */
96 #define SMWDTHROSC_STCC_PIN 0x00000007 /**< Pin select */
97 /** @} */
98 /*---------------------------------------------------------------------------*/
99 /** \name SMWDTHROSC_STCS register bit masks
100  * @{
101  */
102 #define SMWDTHROSC_STCS_VALID 0x00000001 /**< Capture valid flag */
103 /** @} */
104 /*---------------------------------------------------------------------------*/
105 /** \name SMWDTHROSC_STCV[0:3] register bit masks
106  * @{
107  */
108 #define SMWDTHROSC_STCV0_STCV0 0x000000FF /**< ST capture bits [7:0] */
109 #define SMWDTHROSC_STCV1_STCV1 0x000000FF /**< ST capture bits [15:8] */
110 #define SMWDTHROSC_STCV2_STCV2 0x000000FF /**< ST capture bits [23:16] */
111 #define SMWDTHROSC_STCV3_STCV3 0x000000FF /**< ST capture bits [32:24] */
112 /** @} */
113 
114 #endif /* SMWDTHROSC_H_ */
115 
116 /**
117  * @}
118  * @}
119  */