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Contiki-NG
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Type definitions for the Trace Port Interface (TPI) More...
Data Structures | |
| struct | TPI_Type |
| Structure type to access the Trace Port Interface Register (TPI). More... | |
Macros | |
| #define | TPI_ACPR_PRESCALER_Pos 0U |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
| #define | TPI_SPPR_TXMODE_Pos 0U |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
| #define | TPI_FFSR_FtNonStop_Pos 3U |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_TCPresent_Pos 2U |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_FtStopped_Pos 1U |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FlInProg_Pos 0U |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
| #define | TPI_FFCR_TrigIn_Pos 8U |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_EnFCont_Pos 1U |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Pos 0U |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM2_Pos 16U |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM1_Pos 8U |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM0_Pos 0U |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM2_Pos 16U |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM1_Pos 8U |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM0_Pos 0U |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
| #define | TPI_ITCTRL_Mode_Pos 0U |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
| #define | TPI_DEVID_NRZVALID_Pos 11U |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Pos 10U |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Pos 9U |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_MinBufSz_Pos 6U |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_AsynClkIn_Pos 5U |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_NrTraceInput_Pos 0U |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
| #define | TPI_DEVTYPE_MajorType_Pos 4U |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_SubType_Pos 0U |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
| #define | TPI_ACPR_PRESCALER_Pos 0U |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
| #define | TPI_SPPR_TXMODE_Pos 0U |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
| #define | TPI_FFSR_FtNonStop_Pos 3U |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_TCPresent_Pos 2U |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_FtStopped_Pos 1U |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FlInProg_Pos 0U |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
| #define | TPI_FFCR_TrigIn_Pos 8U |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_EnFCont_Pos 1U |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Pos 0U |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM2_Pos 16U |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM1_Pos 8U |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM0_Pos 0U |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM2_Pos 16U |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM1_Pos 8U |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM0_Pos 0U |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
| #define | TPI_ITCTRL_Mode_Pos 0U |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
| #define | TPI_DEVID_NRZVALID_Pos 11U |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Pos 10U |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Pos 9U |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_MinBufSz_Pos 6U |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_AsynClkIn_Pos 5U |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_NrTraceInput_Pos 0U |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
| #define | TPI_DEVTYPE_MajorType_Pos 4U |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_SubType_Pos 0U |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
| #define | TPI_ACPR_PRESCALER_Pos 0U |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
| #define | TPI_SPPR_TXMODE_Pos 0U |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
| #define | TPI_FFSR_FtNonStop_Pos 3U |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_TCPresent_Pos 2U |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_FtStopped_Pos 1U |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FlInProg_Pos 0U |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
| #define | TPI_FFCR_TrigIn_Pos 8U |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_EnFCont_Pos 1U |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Pos 0U |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM2_Pos 16U |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM1_Pos 8U |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM0_Pos 0U |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM2_Pos 16U |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM1_Pos 8U |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM0_Pos 0U |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
| #define | TPI_ITCTRL_Mode_Pos 0U |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
| #define | TPI_DEVID_NRZVALID_Pos 11U |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Pos 10U |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Pos 9U |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_MinBufSz_Pos 6U |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_AsynClkIn_Pos 5U |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_NrTraceInput_Pos 0U |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
| #define | TPI_DEVTYPE_MajorType_Pos 4U |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_SubType_Pos 0U |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
| #define | TPI_ACPR_PRESCALER_Pos 0U |
| #define | TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
| #define | TPI_SPPR_TXMODE_Pos 0U |
| #define | TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
| #define | TPI_FFSR_FtNonStop_Pos 3U |
| #define | TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
| #define | TPI_FFSR_TCPresent_Pos 2U |
| #define | TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
| #define | TPI_FFSR_FtStopped_Pos 1U |
| #define | TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
| #define | TPI_FFSR_FlInProg_Pos 0U |
| #define | TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
| #define | TPI_FFCR_TrigIn_Pos 8U |
| #define | TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
| #define | TPI_FFCR_EnFCont_Pos 1U |
| #define | TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
| #define | TPI_TRIGGER_TRIGGER_Pos 0U |
| #define | TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
| #define | TPI_FIFO0_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
| #define | TPI_FIFO0_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
| #define | TPI_FIFO0_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
| #define | TPI_FIFO0_ETM2_Pos 16U |
| #define | TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
| #define | TPI_FIFO0_ETM1_Pos 8U |
| #define | TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
| #define | TPI_FIFO0_ETM0_Pos 0U |
| #define | TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
| #define | TPI_ITATBCTR2_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
| #define | TPI_FIFO1_ITM_ATVALID_Pos 29U |
| #define | TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
| #define | TPI_FIFO1_ITM_bytecount_Pos 27U |
| #define | TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
| #define | TPI_FIFO1_ETM_ATVALID_Pos 26U |
| #define | TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
| #define | TPI_FIFO1_ETM_bytecount_Pos 24U |
| #define | TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
| #define | TPI_FIFO1_ITM2_Pos 16U |
| #define | TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
| #define | TPI_FIFO1_ITM1_Pos 8U |
| #define | TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
| #define | TPI_FIFO1_ITM0_Pos 0U |
| #define | TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
| #define | TPI_ITATBCTR0_ATREADY_Pos 0U |
| #define | TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
| #define | TPI_ITCTRL_Mode_Pos 0U |
| #define | TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
| #define | TPI_DEVID_NRZVALID_Pos 11U |
| #define | TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
| #define | TPI_DEVID_MANCVALID_Pos 10U |
| #define | TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
| #define | TPI_DEVID_PTINVALID_Pos 9U |
| #define | TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
| #define | TPI_DEVID_MinBufSz_Pos 6U |
| #define | TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
| #define | TPI_DEVID_AsynClkIn_Pos 5U |
| #define | TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
| #define | TPI_DEVID_NrTraceInput_Pos 0U |
| #define | TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
| #define | TPI_DEVTYPE_MajorType_Pos 4U |
| #define | TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
| #define | TPI_DEVTYPE_SubType_Pos 0U |
| #define | TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
Type definitions for the Trace Port Interface (TPI)
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 997 of file core_sc300.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1015 of file core_cm3.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1076 of file core_cm4.h.
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
Definition at line 1281 of file core_cm7.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 996 of file core_sc300.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1014 of file core_cm3.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1075 of file core_cm4.h.
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
Definition at line 1280 of file core_cm7.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1097 of file core_sc300.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1115 of file core_cm3.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1176 of file core_cm4.h.
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
Definition at line 1381 of file core_cm7.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1096 of file core_sc300.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1114 of file core_cm3.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1175 of file core_cm4.h.
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
Definition at line 1380 of file core_cm7.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1088 of file core_sc300.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1106 of file core_cm3.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1167 of file core_cm4.h.
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
Definition at line 1372 of file core_cm7.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1087 of file core_sc300.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1105 of file core_cm3.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1166 of file core_cm4.h.
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
Definition at line 1371 of file core_cm7.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1094 of file core_sc300.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1112 of file core_cm3.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1173 of file core_cm4.h.
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
Definition at line 1378 of file core_cm7.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1093 of file core_sc300.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1111 of file core_cm3.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1172 of file core_cm4.h.
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
Definition at line 1377 of file core_cm7.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1100 of file core_sc300.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1118 of file core_cm3.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1179 of file core_cm4.h.
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
Definition at line 1384 of file core_cm7.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1099 of file core_sc300.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1117 of file core_cm3.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1178 of file core_cm4.h.
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
Definition at line 1383 of file core_cm7.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1085 of file core_sc300.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1103 of file core_cm3.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1164 of file core_cm4.h.
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
Definition at line 1369 of file core_cm7.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1084 of file core_sc300.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1102 of file core_cm3.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1163 of file core_cm4.h.
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
Definition at line 1368 of file core_cm7.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1091 of file core_sc300.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1109 of file core_cm3.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1170 of file core_cm4.h.
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
Definition at line 1375 of file core_cm7.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1090 of file core_sc300.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1108 of file core_cm3.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1169 of file core_cm4.h.
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
Definition at line 1374 of file core_cm7.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1104 of file core_sc300.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1122 of file core_cm3.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1183 of file core_cm4.h.
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
Definition at line 1388 of file core_cm7.h.
| #define TPI_DEVTYPE_MajorType_Pos 4U |
TPI DEVTYPE: MajorType Position
Definition at line 1103 of file core_sc300.h.
| #define TPI_DEVTYPE_MajorType_Pos 4U |
TPI DEVTYPE: MajorType Position
Definition at line 1121 of file core_cm3.h.
| #define TPI_DEVTYPE_MajorType_Pos 4U |
TPI DEVTYPE: MajorType Position
Definition at line 1182 of file core_cm4.h.
| #define TPI_DEVTYPE_MajorType_Pos 4U |
TPI DEVTYPE: MajorType Position
Definition at line 1387 of file core_cm7.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1107 of file core_sc300.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1125 of file core_cm3.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1186 of file core_cm4.h.
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
Definition at line 1391 of file core_cm7.h.
| #define TPI_DEVTYPE_SubType_Pos 0U |
TPI DEVTYPE: SubType Position
Definition at line 1106 of file core_sc300.h.
| #define TPI_DEVTYPE_SubType_Pos 0U |
TPI DEVTYPE: SubType Position
Definition at line 1124 of file core_cm3.h.
| #define TPI_DEVTYPE_SubType_Pos 0U |
TPI DEVTYPE: SubType Position
Definition at line 1185 of file core_cm4.h.
| #define TPI_DEVTYPE_SubType_Pos 0U |
TPI DEVTYPE: SubType Position
Definition at line 1390 of file core_cm7.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1021 of file core_sc300.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1039 of file core_cm3.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1100 of file core_cm4.h.
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
Definition at line 1305 of file core_cm7.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1020 of file core_sc300.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1038 of file core_cm3.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1099 of file core_cm4.h.
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
Definition at line 1304 of file core_cm7.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1018 of file core_sc300.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1036 of file core_cm3.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1097 of file core_cm4.h.
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
Definition at line 1302 of file core_cm7.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1017 of file core_sc300.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1035 of file core_cm3.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1096 of file core_cm4.h.
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
Definition at line 1301 of file core_cm7.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1014 of file core_sc300.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1032 of file core_cm3.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1093 of file core_cm4.h.
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
Definition at line 1298 of file core_cm7.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1013 of file core_sc300.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1031 of file core_cm3.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1092 of file core_cm4.h.
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
Definition at line 1297 of file core_cm7.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1005 of file core_sc300.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1023 of file core_cm3.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1084 of file core_cm4.h.
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
Definition at line 1289 of file core_cm7.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1004 of file core_sc300.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1022 of file core_cm3.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1083 of file core_cm4.h.
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
Definition at line 1288 of file core_cm7.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1011 of file core_sc300.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1029 of file core_cm3.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1090 of file core_cm4.h.
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
Definition at line 1295 of file core_cm7.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1010 of file core_sc300.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1028 of file core_cm3.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1089 of file core_cm4.h.
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
Definition at line 1294 of file core_cm7.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1008 of file core_sc300.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1026 of file core_cm3.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1087 of file core_cm4.h.
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
Definition at line 1292 of file core_cm7.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1007 of file core_sc300.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1025 of file core_cm3.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1086 of file core_cm4.h.
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
Definition at line 1291 of file core_cm7.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1047 of file core_sc300.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1065 of file core_cm3.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1126 of file core_cm4.h.
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
Definition at line 1331 of file core_cm7.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1046 of file core_sc300.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1064 of file core_cm3.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1125 of file core_cm4.h.
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
Definition at line 1330 of file core_cm7.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1044 of file core_sc300.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1062 of file core_cm3.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1123 of file core_cm4.h.
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
Definition at line 1328 of file core_cm7.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1043 of file core_sc300.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1061 of file core_cm3.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1122 of file core_cm4.h.
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
Definition at line 1327 of file core_cm7.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1041 of file core_sc300.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1059 of file core_cm3.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1120 of file core_cm4.h.
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
Definition at line 1325 of file core_cm7.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1040 of file core_sc300.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1058 of file core_cm3.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1119 of file core_cm4.h.
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
Definition at line 1324 of file core_cm7.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1035 of file core_sc300.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1053 of file core_cm3.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1114 of file core_cm4.h.
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
Definition at line 1319 of file core_cm7.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1034 of file core_sc300.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1052 of file core_cm3.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1113 of file core_cm4.h.
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
Definition at line 1318 of file core_cm7.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1038 of file core_sc300.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1056 of file core_cm3.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1117 of file core_cm4.h.
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
Definition at line 1322 of file core_cm7.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1037 of file core_sc300.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1055 of file core_cm3.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1116 of file core_cm4.h.
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
Definition at line 1321 of file core_cm7.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1029 of file core_sc300.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1047 of file core_cm3.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1108 of file core_cm4.h.
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
Definition at line 1313 of file core_cm7.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1028 of file core_sc300.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1046 of file core_cm3.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1107 of file core_cm4.h.
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
Definition at line 1312 of file core_cm7.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1032 of file core_sc300.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1050 of file core_cm3.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1111 of file core_cm4.h.
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
Definition at line 1316 of file core_cm7.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1031 of file core_sc300.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1049 of file core_cm3.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1110 of file core_cm4.h.
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
Definition at line 1315 of file core_cm7.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1061 of file core_sc300.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1079 of file core_cm3.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1140 of file core_cm4.h.
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
Definition at line 1345 of file core_cm7.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1060 of file core_sc300.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1078 of file core_cm3.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1139 of file core_cm4.h.
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
Definition at line 1344 of file core_cm7.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1064 of file core_sc300.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1082 of file core_cm3.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1143 of file core_cm4.h.
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
Definition at line 1348 of file core_cm7.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1063 of file core_sc300.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1081 of file core_cm3.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1142 of file core_cm4.h.
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
Definition at line 1347 of file core_cm7.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1073 of file core_sc300.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1091 of file core_cm3.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1152 of file core_cm4.h.
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
Definition at line 1357 of file core_cm7.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1072 of file core_sc300.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1090 of file core_cm3.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1151 of file core_cm4.h.
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
Definition at line 1356 of file core_cm7.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1070 of file core_sc300.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1088 of file core_cm3.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1149 of file core_cm4.h.
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
Definition at line 1354 of file core_cm7.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1069 of file core_sc300.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1087 of file core_cm3.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1148 of file core_cm4.h.
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
Definition at line 1353 of file core_cm7.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1067 of file core_sc300.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1085 of file core_cm3.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1146 of file core_cm4.h.
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
Definition at line 1351 of file core_cm7.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1066 of file core_sc300.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1084 of file core_cm3.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1145 of file core_cm4.h.
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
Definition at line 1350 of file core_cm7.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1055 of file core_sc300.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1073 of file core_cm3.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1134 of file core_cm4.h.
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
Definition at line 1339 of file core_cm7.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1054 of file core_sc300.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1072 of file core_cm3.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1133 of file core_cm4.h.
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
Definition at line 1338 of file core_cm7.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1058 of file core_sc300.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1076 of file core_cm3.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1137 of file core_cm4.h.
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
Definition at line 1342 of file core_cm7.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1057 of file core_sc300.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1075 of file core_cm3.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1136 of file core_cm4.h.
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
Definition at line 1341 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 1077 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 1095 of file core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 1156 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) |
TPI ITATBCTR0: ATREADY Mask
Definition at line 1361 of file core_cm7.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0U |
TPI ITATBCTR0: ATREADY Position
Definition at line 1076 of file core_sc300.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0U |
TPI ITATBCTR0: ATREADY Position
Definition at line 1094 of file core_cm3.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0U |
TPI ITATBCTR0: ATREADY Position
Definition at line 1155 of file core_cm4.h.
| #define TPI_ITATBCTR0_ATREADY_Pos 0U |
TPI ITATBCTR0: ATREADY Position
Definition at line 1360 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 1051 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 1069 of file core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 1130 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) |
TPI ITATBCTR2: ATREADY Mask
Definition at line 1335 of file core_cm7.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0U |
TPI ITATBCTR2: ATREADY Position
Definition at line 1050 of file core_sc300.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0U |
TPI ITATBCTR2: ATREADY Position
Definition at line 1068 of file core_cm3.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0U |
TPI ITATBCTR2: ATREADY Position
Definition at line 1129 of file core_cm4.h.
| #define TPI_ITATBCTR2_ATREADY_Pos 0U |
TPI ITATBCTR2: ATREADY Position
Definition at line 1334 of file core_cm7.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1081 of file core_sc300.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1099 of file core_cm3.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1160 of file core_cm4.h.
| #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
Definition at line 1365 of file core_cm7.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1080 of file core_sc300.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1098 of file core_cm3.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1159 of file core_cm4.h.
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
Definition at line 1364 of file core_cm7.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1001 of file core_sc300.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1019 of file core_cm3.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1080 of file core_cm4.h.
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
Definition at line 1285 of file core_cm7.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1000 of file core_sc300.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1018 of file core_cm3.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1079 of file core_cm4.h.
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
Definition at line 1284 of file core_cm7.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1025 of file core_sc300.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1043 of file core_cm3.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1104 of file core_cm4.h.
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
Definition at line 1309 of file core_cm7.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1024 of file core_sc300.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1042 of file core_cm3.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1103 of file core_cm4.h.
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
Definition at line 1308 of file core_cm7.h.
1.8.13