Contiki-NG
arch
cpu
cc26x0-cc13x0
cc13xx-cc26xx-def.h
1
/*
2
* Copyright (c) 2017, George Oikonomou - http://www.spd.gr
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions
7
* are met:
8
*
9
* 1. Redistributions of source code must retain the above copyright
10
* notice, this list of conditions and the following disclaimer.
11
* 2. Redistributions in binary form must reproduce the above copyright
12
* notice, this list of conditions and the following disclaimer in the
13
* documentation and/or other materials provided with the distribution.
14
* 3. Neither the name of the copyright holder nor the names of its
15
* contributors may be used to endorse or promote products derived
16
* from this software without specific prior written permission.
17
*
18
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29
* OF THE POSSIBILITY OF SUCH DAMAGE.
30
*/
31
/*---------------------------------------------------------------------------*/
32
#ifndef CC13XX_CC26XX_DEF_H_
33
#define CC13XX_CC26XX_DEF_H_
34
/*---------------------------------------------------------------------------*/
35
#include "
cm3/cm3-def.h
"
36
/*---------------------------------------------------------------------------*/
37
/* TSCH related defines */
38
39
/* 2 bytes header, 4 bytes CRC */
40
#define CC13XX_RADIO_PHY_OVERHEAD 6
41
/* 3 bytes preamble, 3 bytes sync */
42
#define CC13XX_RADIO_PHY_HEADER_LEN 6
43
/* The default data rate is 50 kbps */
44
#define CC13XX_RADIO_BIT_RATE 50000
45
46
/* 1 len byte, 2 bytes CRC */
47
#define CC26XX_RADIO_PHY_OVERHEAD 3
48
/* 4 bytes preamble, 1 byte sync */
49
#define CC26XX_RADIO_PHY_HEADER_LEN 5
50
/* The fixed data rate is 250 kbps */
51
#define CC26XX_RADIO_BIT_RATE 250000
52
53
#if CPU_FAMILY_CC13XX
54
#define RADIO_PHY_HEADER_LEN CC13XX_RADIO_PHY_HEADER_LEN
55
#define RADIO_PHY_OVERHEAD CC13XX_RADIO_PHY_OVERHEAD
56
#define RADIO_BIT_RATE CC13XX_RADIO_BIT_RATE
57
58
/* The TSCH default slot length of 10ms is too short, use custom one instead */
59
#ifndef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
60
#define TSCH_CONF_DEFAULT_TIMESLOT_TIMING tsch_timing_cc13xx_50kbps
61
#endif
/* TSCH_CONF_DEFAULT_TIMESLOT_TIMING */
62
63
/* Symbol for the custom TSCH timeslot timing template */
64
#define TSCH_CONF_ARCH_HDR_PATH "rf-core/cc13xx-50kbps-tsch.h"
65
66
#else
67
#define RADIO_PHY_HEADER_LEN CC26XX_RADIO_PHY_HEADER_LEN
68
#define RADIO_PHY_OVERHEAD CC26XX_RADIO_PHY_OVERHEAD
69
#define RADIO_BIT_RATE CC26XX_RADIO_BIT_RATE
70
#endif
71
72
#define RADIO_BYTE_AIR_TIME (1000000 / (RADIO_BIT_RATE / 8))
73
74
/* Delay between GO signal and SFD */
75
#define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(RADIO_PHY_HEADER_LEN * RADIO_BYTE_AIR_TIME))
76
/* Delay between GO signal and start listening.
77
* This value is so small because the radio is constantly on within each timeslot. */
78
#define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(15))
79
/* Delay between the SFD finishes arriving and it is detected in software. */
80
#define RADIO_DELAY_BEFORE_DETECT ((unsigned)US_TO_RTIMERTICKS(352))
81
82
/* Timer conversion; radio is running at 4 MHz */
83
#define RADIO_TIMER_SECOND 4000000u
84
#if (RTIMER_SECOND % 256) || (RADIO_TIMER_SECOND % 256)
85
#error RADIO_TO_RTIMER macro must be fixed!
86
#endif
87
#define RADIO_TO_RTIMER(X) ((uint32_t)(((uint64_t)(X) * (RTIMER_SECOND / 256)) / (RADIO_TIMER_SECOND / 256)))
88
#define USEC_TO_RADIO(X) ((X) * 4)
89
90
/* Do not turn off TSCH within a timeslot: not enough time */
91
#define TSCH_CONF_RADIO_ON_DURING_TIMESLOT 1
92
93
/* Disable TSCH frame filtering */
94
#define TSCH_CONF_HW_FRAME_FILTERING 0
95
96
/* Use hardware timestamps */
97
#ifndef TSCH_CONF_RESYNC_WITH_SFD_TIMESTAMPS
98
#define TSCH_CONF_RESYNC_WITH_SFD_TIMESTAMPS 1
99
#define TSCH_CONF_TIMESYNC_REMOVE_JITTER 0
100
#endif
101
102
#ifndef TSCH_CONF_BASE_DRIFT_PPM
103
#if CPU_FAMILY_CC13XX
104
/* The drift compared to "true" 40ms slots.
105
* Enable adaptive sync to enable compensation for this.
106
* Slot length 40000 usec
107
* 1311 ticks
108
* Tick duration 30.517578125 usec
109
* Real slot duration 40008.544922 usec
110
* Target - real duration = -8.544922 usec
111
* PPM -8.544922 / 40000 = -0.000214
112
*/
113
#define TSCH_CONF_BASE_DRIFT_PPM -214
114
#else
/* CPU_FAMILY_CC13XX */
115
/* The drift compared to "true" 10ms slots.
116
* Enable adaptive sync to enable compensation for this.
117
* Slot length 10000 usec
118
* 328 ticks
119
* Tick duration 30.517578125 usec
120
* Real slot duration 10009.765625 usec
121
* Target - real duration = -9.765625 usec
122
* TSCH_CONF_BASE_DRIFT_PPM -977
123
*/
124
#define TSCH_CONF_BASE_DRIFT_PPM -977
125
#endif
/* CPU_FAMILY_CC13XX */
126
#endif
/* TSCH_CONF_BASE_DRIFT_PPM */
127
128
/* 10 times per second */
129
#ifndef TSCH_CONF_CHANNEL_SCAN_DURATION
130
#define TSCH_CONF_CHANNEL_SCAN_DURATION (CLOCK_SECOND / 10)
131
#endif
132
133
/* Increase this from the default 100 to improve TSCH association speed on this platform */
134
#ifndef TSCH_CONF_ASSOCIATION_POLL_FREQUENCY
135
#define TSCH_CONF_ASSOCIATION_POLL_FREQUENCY 1000
136
#endif
137
138
/* Slightly reduce the TSCH guard time (from 2200 usec to 1800 usec) to make sure
139
* the CC26xx radio has sufficient time to start up. */
140
#ifndef TSCH_CONF_RX_WAIT
141
#define TSCH_CONF_RX_WAIT 1800
142
#endif
143
/*---------------------------------------------------------------------------*/
144
#define RTIMER_ARCH_SECOND 65536
145
/*---------------------------------------------------------------------------*/
146
/* Path to CMSIS header */
147
#define CMSIS_CONF_HEADER_PATH "cc13x0-cc26x0-cm3.h"
148
149
/* Path to headers with implementation of mutexes, atomic and memory barriers */
150
#define MUTEX_CONF_ARCH_HEADER_PATH "mutex-cortex.h"
151
#define ATOMIC_CONF_ARCH_HEADER_PATH "atomic-cortex.h"
152
#define MEMORY_BARRIER_CONF_ARCH_HEADER_PATH "memory-barrier-cortex.h"
153
/*---------------------------------------------------------------------------*/
154
#define GPIO_HAL_CONF_ARCH_HDR_PATH "dev/gpio-hal-arch.h"
155
#define GPIO_HAL_CONF_ARCH_SW_TOGGLE 0
156
#define GPIO_HAL_CONF_PORT_PIN_NUMBERING 0
157
/*---------------------------------------------------------------------------*/
158
#define SPI_CONF_CONTROLLER_COUNT 2
159
/*---------------------------------------------------------------------------*/
160
#endif
/* CC13XX_CC26XX_DEF_H_ */
161
/*---------------------------------------------------------------------------*/
cm3-def.h
Compiler and data type definitions for all CM3-based CPUs.
Generated on Sat May 30 2020 17:03:40 for Contiki-NG by
1.8.13