Contiki-NG
aes.h
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1 /*
2  * Original file:
3  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4  * All rights reserved.
5  *
6  * Port to Contiki:
7  * Copyright (c) 2013, ADVANSEE - http://www.advansee.com/
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  * notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the distribution.
18  *
19  * 3. Neither the name of the copyright holder nor the names of its
20  * contributors may be used to endorse or promote products derived
21  * from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
34  * OF THE POSSIBILITY OF SUCH DAMAGE.
35  */
36 /**
37  * \addtogroup cc2538-crypto
38  * @{
39  *
40  * \defgroup cc2538-aes cc2538 AES
41  *
42  * Driver for the cc2538 AES modes of the security core
43  * @{
44  *
45  * \file
46  * Header file for the cc2538 AES driver
47  */
48 #ifndef AES_H_
49 #define AES_H_
50 
51 #include "contiki.h"
52 #include "dev/crypto.h"
53 
54 #include <stdbool.h>
55 #include <stdint.h>
56 /*---------------------------------------------------------------------------*/
57 /** \name AES register offsets
58  * @{
59  */
60 #define AES_DMAC_CH0_CTRL 0x4008B000 /**< Channel 0 control */
61 #define AES_DMAC_CH0_EXTADDR 0x4008B004 /**< Channel 0 external address */
62 #define AES_DMAC_CH0_DMALENGTH 0x4008B00C /**< Channel 0 DMA length */
63 #define AES_DMAC_STATUS 0x4008B018 /**< DMAC status */
64 #define AES_DMAC_SWRES 0x4008B01C /**< DMAC software reset */
65 #define AES_DMAC_CH1_CTRL 0x4008B020 /**< Channel 1 control */
66 #define AES_DMAC_CH1_EXTADDR 0x4008B024 /**< Channel 1 external address */
67 #define AES_DMAC_CH1_DMALENGTH 0x4008B02C /**< Channel 1 DMA length */
68 #define AES_DMAC_MST_RUNPARAMS 0x4008B078 /**< DMAC master run-time parameters */
69 #define AES_DMAC_PERSR 0x4008B07C /**< DMAC port error raw status */
70 #define AES_DMAC_OPTIONS 0x4008B0F8 /**< DMAC options */
71 #define AES_DMAC_VERSION 0x4008B0FC /**< DMAC version */
72 #define AES_KEY_STORE_WRITE_AREA \
73  0x4008B400 /**< Key store write area */
74 #define AES_KEY_STORE_WRITTEN_AREA \
75  0x4008B404 /**< Key store written area */
76 #define AES_KEY_STORE_SIZE 0x4008B408 /**< Key store size */
77 #define AES_KEY_STORE_READ_AREA 0x4008B40C /**< Key store read area */
78 #define AES_AES_KEY2_0 0x4008B500 /**< AES_KEY2_0 / AES_GHASH_H_IN_0 */
79 #define AES_AES_KEY2_1 0x4008B504 /**< AES_KEY2_1 / AES_GHASH_H_IN_1 */
80 #define AES_AES_KEY2_2 0x4008B508 /**< AES_KEY2_2 / AES_GHASH_H_IN_2 */
81 #define AES_AES_KEY2_3 0x4008B50C /**< AES_KEY2_3 / AES_GHASH_H_IN_3 */
82 #define AES_AES_KEY3_0 0x4008B510 /**< AES_KEY3_0 / AES_KEY2_4 */
83 #define AES_AES_KEY3_1 0x4008B514 /**< AES_KEY3_1 / AES_KEY2_5 */
84 #define AES_AES_KEY3_2 0x4008B518 /**< AES_KEY3_2 / AES_KEY2_6 */
85 #define AES_AES_KEY3_3 0x4008B51C /**< AES_KEY3_3 / AES_KEY2_7 */
86 #define AES_AES_IV_0 0x4008B540 /**< AES initialization vector */
87 #define AES_AES_IV_1 0x4008B544 /**< AES initialization vector */
88 #define AES_AES_IV_2 0x4008B548 /**< AES initialization vector */
89 #define AES_AES_IV_3 0x4008B54C /**< AES initialization vector */
90 #define AES_AES_CTRL 0x4008B550 /**< AES input/output buffer control and mode */
91 #define AES_AES_C_LENGTH_0 0x4008B554 /**< AES crypto length (LSW) */
92 #define AES_AES_C_LENGTH_1 0x4008B558 /**< AES crypto length (MSW) */
93 #define AES_AES_AUTH_LENGTH 0x4008B55C /**< Authentication length */
94 #define AES_AES_DATA_IN_OUT_0 0x4008B560 /**< Data input/output */
95 #define AES_AES_DATA_IN_OUT_1 0x4008B564 /**< Data Input/Output */
96 #define AES_AES_DATA_IN_OUT_2 0x4008B568 /**< Data Input/Output */
97 #define AES_AES_DATA_IN_OUT_3 0x4008B56C /**< Data Input/Output */
98 #define AES_AES_TAG_OUT_0 0x4008B570 /**< TAG */
99 #define AES_AES_TAG_OUT_1 0x4008B574 /**< TAG */
100 #define AES_AES_TAG_OUT_2 0x4008B578 /**< TAG */
101 #define AES_AES_TAG_OUT_3 0x4008B57C /**< TAG */
102 #define AES_HASH_DATA_IN_0 0x4008B600 /**< HASH data input */
103 #define AES_HASH_DATA_IN_1 0x4008B604 /**< HASH data input */
104 #define AES_HASH_DATA_IN_2 0x4008B608 /**< HASH data input */
105 #define AES_HASH_DATA_IN_3 0x4008B60C /**< HASH data input */
106 #define AES_HASH_DATA_IN_4 0x4008B610 /**< HASH data input */
107 #define AES_HASH_DATA_IN_5 0x4008B614 /**< HASH data input */
108 #define AES_HASH_DATA_IN_6 0x4008B618 /**< HASH data input */
109 #define AES_HASH_DATA_IN_7 0x4008B61C /**< HASH data input */
110 #define AES_HASH_DATA_IN_8 0x4008B620 /**< HASH data input */
111 #define AES_HASH_DATA_IN_9 0x4008B624 /**< HASH data input */
112 #define AES_HASH_DATA_IN_10 0x4008B628 /**< HASH data input */
113 #define AES_HASH_DATA_IN_11 0x4008B62C /**< HASH data input */
114 #define AES_HASH_DATA_IN_12 0x4008B630 /**< HASH data input */
115 #define AES_HASH_DATA_IN_13 0x4008B634 /**< HASH data input */
116 #define AES_HASH_DATA_IN_14 0x4008B638 /**< HASH data input */
117 #define AES_HASH_DATA_IN_15 0x4008B63C /**< HASH data input */
118 #define AES_HASH_IO_BUF_CTRL 0x4008B640 /**< Input/output buffer control and status */
119 #define AES_HASH_MODE_IN 0x4008B644 /**< Hash mode */
120 #define AES_HASH_LENGTH_IN_L 0x4008B648 /**< Hash length */
121 #define AES_HASH_LENGTH_IN_H 0x4008B64C /**< Hash length */
122 #define AES_HASH_DIGEST_A 0x4008B650 /**< Hash digest */
123 #define AES_HASH_DIGEST_B 0x4008B654 /**< Hash digest */
124 #define AES_HASH_DIGEST_C 0x4008B658 /**< Hash digest */
125 #define AES_HASH_DIGEST_D 0x4008B65C /**< Hash digest */
126 #define AES_HASH_DIGEST_E 0x4008B660 /**< Hash digest */
127 #define AES_HASH_DIGEST_F 0x4008B664 /**< Hash digest */
128 #define AES_HASH_DIGEST_G 0x4008B668 /**< Hash digest */
129 #define AES_HASH_DIGEST_H 0x4008B66C /**< Hash digest */
130 #define AES_CTRL_ALG_SEL 0x4008B700 /**< Algorithm select */
131 #define AES_CTRL_PROT_EN 0x4008B704 /**< Master PROT privileged access enable */
132 #define AES_CTRL_SW_RESET 0x4008B740 /**< Software reset */
133 #define AES_CTRL_INT_CFG 0x4008B780 /**< Interrupt configuration */
134 #define AES_CTRL_INT_EN 0x4008B784 /**< Interrupt enable */
135 #define AES_CTRL_INT_CLR 0x4008B788 /**< Interrupt clear */
136 #define AES_CTRL_INT_SET 0x4008B78C /**< Interrupt set */
137 #define AES_CTRL_INT_STAT 0x4008B790 /**< Interrupt status */
138 #define AES_CTRL_OPTIONS 0x4008B7F8 /**< Options */
139 #define AES_CTRL_VERSION 0x4008B7FC /**< Version */
140 /** @} */
141 /*---------------------------------------------------------------------------*/
142 /** \name AES_DMAC_CHx_CTRL registers bit fields
143  * @{
144  */
145 #define AES_DMAC_CH_CTRL_PRIO 0x00000002 /**< Channel priority 0: Low 1: High */
146 #define AES_DMAC_CH_CTRL_EN 0x00000001 /**< Channel enable */
147 /** @} */
148 /*---------------------------------------------------------------------------*/
149 /** \name AES_DMAC_CHx_DMALENGTH registers bit fields
150  * @{
151  */
152 #define AES_DMAC_CH_DMALENGTH_DMALEN_M \
153  0x0000FFFF /**< Channel DMA length in bytes mask */
154 #define AES_DMAC_CH_DMALENGTH_DMALEN_S 0 /**< Channel DMA length in bytes shift */
155 /** @} */
156 /*---------------------------------------------------------------------------*/
157 /** \name AES_DMAC_STATUS register bit fields
158  * @{
159  */
160 #define AES_DMAC_STATUS_PORT_ERR \
161  0x00020000 /**< AHB port transfer errors */
162 #define AES_DMAC_STATUS_CH1_ACT 0x00000002 /**< Channel 1 active (DMA transfer on-going) */
163 #define AES_DMAC_STATUS_CH0_ACT 0x00000001 /**< Channel 0 active (DMA transfer on-going) */
164 /** @} */
165 /*---------------------------------------------------------------------------*/
166 /** \name AES_DMAC_SWRES register bit fields
167  * @{
168  */
169 #define AES_DMAC_SWRES_SWRES 0x00000001 /**< Software reset enable */
170 /** @} */
171 /*---------------------------------------------------------------------------*/
172 /** \name AES_DMAC_MST_RUNPARAMS register bit fields
173  * @{
174  */
175 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_4 \
176  (2 << 12) /**< Maximum burst size: 4 bytes */
177 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_8 \
178  (3 << 12) /**< Maximum burst size: 8 bytes */
179 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_16 \
180  (4 << 12) /**< Maximum burst size: 16 bytes */
181 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_32 \
182  (5 << 12) /**< Maximum burst size: 32 bytes */
183 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_64 \
184  (6 << 12) /**< Maximum burst size: 64 bytes */
185 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_M \
186  0x0000F000 /**< Maximum burst size mask */
187 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_S \
188  12 /**< Maximum burst size shift */
189 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_IDLE_EN \
190  0x00000800 /**< Idle insertion between bursts */
191 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_INCR_EN \
192  0x00000400 /**< Fixed-length burst or single transfers */
193 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_LOCK_EN \
194  0x00000200 /**< Locked transfers */
195 #define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BIGEND \
196  0x00000100 /**< Big endian AHB master */
197 /** @} */
198 /*---------------------------------------------------------------------------*/
199 /** \name AES_DMAC_PERSR register bit fields
200  * @{
201  */
202 #define AES_DMAC_PERSR_PORT1_AHB_ERROR \
203  0x00001000 /**< AHB bus error */
204 #define AES_DMAC_PERSR_PORT1_CHANNEL \
205  0x00000200 /**< Last serviced channel (0 or 1) */
206 /** @} */
207 /*---------------------------------------------------------------------------*/
208 /** \name AES_DMAC_OPTIONS register bit fields
209  * @{
210  */
211 #define AES_DMAC_OPTIONS_NR_OF_CHANNELS_M \
212  0x00000F00 /**< Number of channels implemented mask */
213 #define AES_DMAC_OPTIONS_NR_OF_CHANNELS_S \
214  8 /**< Number of channels implemented shift */
215 #define AES_DMAC_OPTIONS_NR_OF_PORTS_M \
216  0x00000007 /**< Number of ports implemented mask */
217 #define AES_DMAC_OPTIONS_NR_OF_PORTS_S 0 /**< Number of ports implemented shift */
218 /** @} */
219 /*---------------------------------------------------------------------------*/
220 /** \name AES_DMAC_VERSION register bit fields
221  * @{
222  */
223 #define AES_DMAC_VERSION_HW_MAJOR_VERSION_M \
224  0x0F000000 /**< Major version number mask */
225 #define AES_DMAC_VERSION_HW_MAJOR_VERSION_S \
226  24 /**< Major version number shift */
227 #define AES_DMAC_VERSION_HW_MINOR_VERSION_M \
228  0x00F00000 /**< Minor version number mask */
229 #define AES_DMAC_VERSION_HW_MINOR_VERSION_S \
230  20 /**< Minor version number shift */
231 #define AES_DMAC_VERSION_HW_PATCH_LEVEL_M \
232  0x000F0000 /**< Patch level mask */
233 #define AES_DMAC_VERSION_HW_PATCH_LEVEL_S \
234  16 /**< Patch level shift */
235 #define AES_DMAC_VERSION_EIP_NUMBER_COMPL_M \
236  0x0000FF00 /**< EIP_NUMBER 1's complement mask */
237 #define AES_DMAC_VERSION_EIP_NUMBER_COMPL_S \
238  8 /**< EIP_NUMBER 1's complement shift */
239 #define AES_DMAC_VERSION_EIP_NUMBER_M \
240  0x000000FF /**< DMAC EIP-number mask */
241 #define AES_DMAC_VERSION_EIP_NUMBER_S 0 /**< DMAC EIP-number shift */
242 /** @} */
243 /*---------------------------------------------------------------------------*/
244 /** \name AES_KEY_STORE_SIZE register bit fields
245  * @{
246  */
247 #define AES_KEY_STORE_SIZE_KEY_SIZE_128 1 /**< Key size: 128 bits */
248 #define AES_KEY_STORE_SIZE_KEY_SIZE_192 2 /**< Key size: 192 bits */
249 #define AES_KEY_STORE_SIZE_KEY_SIZE_256 3 /**< Key size: 256 bits */
250 #define AES_KEY_STORE_SIZE_KEY_SIZE_M \
251  0x00000003 /**< Key size mask */
252 #define AES_KEY_STORE_SIZE_KEY_SIZE_S 0 /**< Key size shift */
253 /** @} */
254 /*---------------------------------------------------------------------------*/
255 /** \name AES_KEY_STORE_READ_AREA register bit fields
256  * @{
257  */
258 #define AES_KEY_STORE_READ_AREA_BUSY \
259  0x80000000 /**< Key store operation busy */
260 #define AES_KEY_STORE_READ_AREA_RAM_AREA_M \
261  0x0000000F /**< Key store RAM area select mask */
262 #define AES_KEY_STORE_READ_AREA_RAM_AREA_S \
263  0 /**< Key store RAM area select shift */
264 /** @} */
265 /*---------------------------------------------------------------------------*/
266 /** \name AES_AES_CTRL register bit fields
267  * @{
268  */
269 #define AES_AES_CTRL_CONTEXT_READY \
270  0x80000000 /**< Context data registers can be overwritten */
271 #define AES_AES_CTRL_SAVED_CONTEXT_READY \
272  0x40000000 /**< AES auth. TAG and/or IV block(s) available */
273 #define AES_AES_CTRL_SAVE_CONTEXT \
274  0x20000000 /**< Auth. TAG or result IV needs to be stored */
275 #define AES_AES_CTRL_CCM_M_M 0x01C00000 /**< CCM auth. field length mask */
276 #define AES_AES_CTRL_CCM_M_S 22 /**< CCM auth. field length shift */
277 #define AES_AES_CTRL_CCM_L_M 0x00380000 /**< CCM length field width mask */
278 #define AES_AES_CTRL_CCM_L_S 19 /**< CCM length field width shift */
279 #define AES_AES_CTRL_CCM 0x00040000 /**< AES-CCM mode */
280 #define AES_AES_CTRL_GCM 0x00030000 /**< AES-GCM mode */
281 #define AES_AES_CTRL_CBC_MAC 0x00008000 /**< AES-CBC MAC mode */
282 #define AES_AES_CTRL_CTR_WIDTH_32 (0 << 7) /**< CTR counter width: 32 bits */
283 #define AES_AES_CTRL_CTR_WIDTH_64 (1 << 7) /**< CTR counter width: 64 bits */
284 #define AES_AES_CTRL_CTR_WIDTH_96 (2 << 7) /**< CTR counter width: 96 bits */
285 #define AES_AES_CTRL_CTR_WIDTH_128 \
286  (3 << 7) /**< CTR counter width: 128 bits */
287 #define AES_AES_CTRL_CTR_WIDTH_M \
288  0x00000180 /**< CTR counter width mask */
289 #define AES_AES_CTRL_CTR_WIDTH_S 7 /**< CTR counter width shift */
290 #define AES_AES_CTRL_CTR 0x00000040 /**< AES-CTR mode */
291 #define AES_AES_CTRL_CBC 0x00000020 /**< AES-CBC mode */
292 #define AES_AES_CTRL_KEY_SIZE_128 (1 << 3) /**< Key size: 128 bits */
293 #define AES_AES_CTRL_KEY_SIZE_192 (2 << 3) /**< Key size: 192 bits */
294 #define AES_AES_CTRL_KEY_SIZE_256 (3 << 3) /**< Key size: 256 bits */
295 #define AES_AES_CTRL_KEY_SIZE_M 0x00000018 /**< Key size mask */
296 #define AES_AES_CTRL_KEY_SIZE_S 3 /**< Key size shift */
297 #define AES_AES_CTRL_DIRECTION_ENCRYPT \
298  0x00000004 /**< Encrypt */
299 #define AES_AES_CTRL_INPUT_READY \
300  0x00000002 /**< AES input buffer empty */
301 #define AES_AES_CTRL_OUTPUT_READY \
302  0x00000001 /**< AES output block available */
303 /** @} */
304 /*---------------------------------------------------------------------------*/
305 /** \name AES_AES_C_LENGTH_1 register bit fields
306  * @{
307  */
308 #define AES_AES_C_LENGTH_1_C_LENGTH_M \
309  0x1FFFFFFF /**< Crypto length bits [60:32] mask */
310 #define AES_AES_C_LENGTH_1_C_LENGTH_S 0 /**< Crypto length bits [60:32] shift */
311 /** @} */
312 /*---------------------------------------------------------------------------*/
313 /** \name AES_HASH_IO_BUF_CTRL register bit fields
314  * @{
315  */
316 #define AES_HASH_IO_BUF_CTRL_PAD_DMA_MESSAGE \
317  0x00000080 /**< Hash engine message padding required */
318 #define AES_HASH_IO_BUF_CTRL_GET_DIGEST \
319  0x00000040 /**< Hash engine digest requested */
320 #define AES_HASH_IO_BUF_CTRL_PAD_MESSAGE \
321  0x00000020 /**< Last message data in HASH_DATA_IN, apply hash padding */
322 #define AES_HASH_IO_BUF_CTRL_RFD_IN \
323  0x00000004 /**< Hash engine input buffer can accept new data */
324 #define AES_HASH_IO_BUF_CTRL_DATA_IN_AV \
325  0x00000002 /**< Start processing HASH_DATA_IN data */
326 #define AES_HASH_IO_BUF_CTRL_OUTPUT_FULL \
327  0x00000001 /**< Output buffer registers available */
328 /** @} */
329 /*---------------------------------------------------------------------------*/
330 /** \name AES_HASH_MODE_IN register bit fields
331  * @{
332  */
333 #define AES_HASH_MODE_IN_SHA256_MODE \
334  0x00000008 /**< Hash mode */
335 #define AES_HASH_MODE_IN_NEW_HASH \
336  0x00000001 /**< New hash session */
337 /** @} */
338 /*---------------------------------------------------------------------------*/
339 /** \name AES_CTRL_ALG_SEL register bit fields
340  * @{
341  */
342 #define AES_CTRL_ALG_SEL_TAG 0x80000000 /**< DMA operation includes TAG */
343 #define AES_CTRL_ALG_SEL_HASH 0x00000004 /**< Select hash engine as DMA destination */
344 #define AES_CTRL_ALG_SEL_AES 0x00000002 /**< Select AES engine as DMA source/destination */
345 #define AES_CTRL_ALG_SEL_KEYSTORE \
346  0x00000001 /**< Select Key Store as DMA destination */
347 /** @} */
348 /*---------------------------------------------------------------------------*/
349 /** \name AES_CTRL_PROT_EN register bit fields
350  * @{
351  */
352 #define AES_CTRL_PROT_EN_PROT_EN \
353  0x00000001 /**< m_h_prot[1] asserted for DMA reads towards key store */
354 /** @} */
355 /*---------------------------------------------------------------------------*/
356 /** \name AES_CTRL_SW_RESET register bit fields
357  * @{
358  */
359 #define AES_CTRL_SW_RESET_SW_RESET \
360  0x00000001 /**< Reset master control and key store */
361 /** @} */
362 /*---------------------------------------------------------------------------*/
363 /** \name AES_CTRL_INT_CFG register bit fields
364  * @{
365  */
366 #define AES_CTRL_INT_CFG_LEVEL 0x00000001 /**< Level interrupt type */
367 /** @} */
368 /*---------------------------------------------------------------------------*/
369 /** \name AES_CTRL_INT_EN register bit fields
370  * @{
371  */
372 #define AES_CTRL_INT_EN_DMA_IN_DONE \
373  0x00000002 /**< DMA input done interrupt enabled */
374 #define AES_CTRL_INT_EN_RESULT_AV \
375  0x00000001 /**< Result available interrupt enabled */
376 /** @} */
377 /*---------------------------------------------------------------------------*/
378 /** \name AES_CTRL_INT_CLR register bit fields
379  * @{
380  */
381 #define AES_CTRL_INT_CLR_DMA_BUS_ERR \
382  0x80000000 /**< Clear DMA bus error status */
383 #define AES_CTRL_INT_CLR_KEY_ST_WR_ERR \
384  0x40000000 /**< Clear key store write error status */
385 #define AES_CTRL_INT_CLR_KEY_ST_RD_ERR \
386  0x20000000 /**< Clear key store read error status */
387 #define AES_CTRL_INT_CLR_DMA_IN_DONE \
388  0x00000002 /**< Clear DMA in done interrupt */
389 #define AES_CTRL_INT_CLR_RESULT_AV \
390  0x00000001 /**< Clear result available interrupt */
391 /** @} */
392 /*---------------------------------------------------------------------------*/
393 /** \name AES_CTRL_INT_SET register bit fields
394  * @{
395  */
396 #define AES_CTRL_INT_SET_DMA_IN_DONE \
397  0x00000002 /**< Set DMA data in done interrupt */
398 #define AES_CTRL_INT_SET_RESULT_AV \
399  0x00000001 /**< Set result available interrupt */
400 /** @} */
401 /*---------------------------------------------------------------------------*/
402 /** \name AES_CTRL_INT_STAT register bit fields
403  * @{
404  */
405 #define AES_CTRL_INT_STAT_DMA_BUS_ERR \
406  0x80000000 /**< DMA bus error detected */
407 #define AES_CTRL_INT_STAT_KEY_ST_WR_ERR \
408  0x40000000 /**< Write error detected */
409 #define AES_CTRL_INT_STAT_KEY_ST_RD_ERR \
410  0x20000000 /**< Read error detected */
411 #define AES_CTRL_INT_STAT_DMA_IN_DONE \
412  0x00000002 /**< DMA data in done interrupt status */
413 #define AES_CTRL_INT_STAT_RESULT_AV \
414  0x00000001 /**< Result available interrupt status */
415 /** @} */
416 /*---------------------------------------------------------------------------*/
417 /** \name AES_CTRL_OPTIONS register bit fields
418  * @{
419  */
420 #define AES_CTRL_OPTIONS_TYPE_M 0xFF000000 /**< Device type mask */
421 #define AES_CTRL_OPTIONS_TYPE_S 24 /**< Device type shift */
422 #define AES_CTRL_OPTIONS_AHBINTERFACE \
423  0x00010000 /**< AHB interface available */
424 #define AES_CTRL_OPTIONS_SHA_256 \
425  0x00000100 /**< The HASH core supports SHA-256 */
426 #define AES_CTRL_OPTIONS_AES_CCM \
427  0x00000080 /**< AES-CCM available as single operation */
428 #define AES_CTRL_OPTIONS_AES_GCM \
429  0x00000040 /**< AES-GCM available as single operation */
430 #define AES_CTRL_OPTIONS_AES_256 \
431  0x00000020 /**< AES core supports 256-bit keys */
432 #define AES_CTRL_OPTIONS_AES_128 \
433  0x00000010 /**< AES core supports 128-bit keys */
434 #define AES_CTRL_OPTIONS_HASH 0x00000004 /**< HASH Core available */
435 #define AES_CTRL_OPTIONS_AES 0x00000002 /**< AES core available */
436 #define AES_CTRL_OPTIONS_KEYSTORE \
437  0x00000001 /**< KEY STORE available */
438 /** @} */
439 /*---------------------------------------------------------------------------*/
440 /** \name AES_CTRL_VERSION register bit fields
441  * @{
442  */
443 #define AES_CTRL_VERSION_MAJOR_VERSION_M \
444  0x0F000000 /**< Major version number mask */
445 #define AES_CTRL_VERSION_MAJOR_VERSION_S \
446  24 /**< Major version number shift */
447 #define AES_CTRL_VERSION_MINOR_VERSION_M \
448  0x00F00000 /**< Minor version number mask */
449 #define AES_CTRL_VERSION_MINOR_VERSION_S \
450  20 /**< Minor version number shift */
451 #define AES_CTRL_VERSION_PATCH_LEVEL_M \
452  0x000F0000 /**< Patch level mask */
453 #define AES_CTRL_VERSION_PATCH_LEVEL_S 16 /**< Patch level shift */
454 #define AES_CTRL_VERSION_EIP_NUMBER_COMPL_M \
455  0x0000FF00 /**< EIP_NUMBER 1's complement mask */
456 #define AES_CTRL_VERSION_EIP_NUMBER_COMPL_S \
457  8 /**< EIP_NUMBER 1's complement shift */
458 #define AES_CTRL_VERSION_EIP_NUMBER_M \
459  0x000000FF /**< EIP-120t EIP-number mask */
460 #define AES_CTRL_VERSION_EIP_NUMBER_S 0 /**< EIP-120t EIP-number shift */
461 /** @} */
462 /*---------------------------------------------------------------------------*/
463 /** \name AES drivers return codes
464  * @{
465  */
466 #define AES_KEYSTORE_READ_ERROR 5
467 #define AES_KEYSTORE_WRITE_ERROR 6
468 #define AES_AUTHENTICATION_FAILED 7
469 /** @} */
470 /*---------------------------------------------------------------------------*/
471 /** \name AES constants
472  * @{
473  */
474 #define AES_KEY_AREAS 8
475 #define AES_BLOCK_LEN (128 / 8)
476 #define AES_IV_LEN AES_BLOCK_LEN
477 #define AES_TAG_LEN AES_BLOCK_LEN
478 /** @} */
479 /*---------------------------------------------------------------------------*/
480 /** \name AES functions
481  * @{
482  */
483 
484 /** \brief Writes keys into the Key RAM
485  * \param keys Pointer to AES Keys
486  * \param key_size Key size: \c AES_KEY_STORE_SIZE_KEY_SIZE_x
487  * \param count Number of keys (1 to \c AES_KEY_AREAS - \p start_area for
488  * 128-bit keys, 1 to (\c AES_KEY_AREAS - \p start_area) / 2 for 192- and
489  * 256-bit keys)
490  * \param start_area Start area in Key RAM where to store the keys (0 to
491  * \c AES_KEY_AREAS - 1, must be even for 192- and 256-bit keys)
492  * \return \c CRYPTO_SUCCESS if successful, or CRYPTO/AES error code
493  * \note Calling this function with a value of \p key_size different from the
494  * one passed for the previous calls causes the deletion of all previously
495  * stored keys.
496  */
497 uint8_t aes_load_keys(const void *keys, uint8_t key_size, uint8_t count,
498  uint8_t start_area);
499 
500 /** \brief Starts an AES authentication/crypto operation
501  * \param ctrl Contents of the \c AES_AES_CTRL register
502  * \param key_area Area in Key RAM where the key is stored (0 to
503  * \c AES_KEY_AREAS - 1)
504  * \param iv Pointer to 128-bit initialization vector, or \c NULL
505  * \param adata Pointer to additional authenticated data in SRAM, or \c NULL
506  * \param adata_len Length of additional authenticated data in octets, or \c 0
507  * \param data_in Pointer to input payload data in SRAM, or \c NULL
508  * \param data_out Pointer to output payload data in SRAM (may be \p data_in),
509  * or \c NULL
510  * \param data_len Length of payload data in octets, or \c 0
511  * \param process Process to be polled upon completion of the operation, or
512  * \c NULL
513  * \return \c CRYPTO_SUCCESS if successful, or CRYPTO/AES error code
514  * \note This function is only supposed to be called by the AES drivers.
515  */
516 uint8_t aes_auth_crypt_start(uint32_t ctrl, uint8_t key_area, const void *iv,
517  const void *adata, uint16_t adata_len,
518  const void *data_in, void *data_out,
519  uint16_t data_len, struct process *process);
520 
521 /** \brief Checks the status of the AES authentication/crypto operation
522  * \retval false Result not yet available, and no error occurred
523  * \retval true Result available, or error occurred
524  * \note This function is only supposed to be called by the AES drivers.
525  */
526 uint8_t aes_auth_crypt_check_status(void);
527 
528 /** \brief Gets the result of the AES authentication/crypto operation
529  * \param iv Pointer to 128-bit result initialization vector, or \c NULL
530  * \param tag Pointer to 128-bit result tag, or \c NULL
531  * \return \c CRYPTO_SUCCESS if successful, or CRYPTO/AES error code
532  * \note This function must be called only after \c aes_auth_crypt_start().
533  * \note This function is only supposed to be called by the AES drivers.
534  */
535 uint8_t aes_auth_crypt_get_result(void *iv, void *tag);
536 
537 /** @} */
538 
539 #endif /* AES_H_ */
540 
541 /**
542  * @}
543  * @}
544  */
aes_auth_crypt_get_result
uint8_t aes_auth_crypt_get_result(void *iv, void *tag)
Gets the result of the AES authentication/crypto operation.
Definition: aes.c:275
crypto.h
Header file for the cc2538 AES/SHA cryptoprocessor driver.
aes_auth_crypt_start
uint8_t aes_auth_crypt_start(uint32_t ctrl, uint8_t key_area, const void *iv, const void *adata, uint16_t adata_len, const void *data_in, void *data_out, uint16_t data_len, struct process *process)
Starts an AES authentication/crypto operation.
Definition: aes.c:156
aes_auth_crypt_check_status
uint8_t aes_auth_crypt_check_status(void)
Checks the status of the AES authentication/crypto operation.
Definition: aes.c:267
aes_load_keys
uint8_t aes_load_keys(const void *keys, uint8_t key_size, uint8_t count, uint8_t start_area)
Writes keys into the Key RAM.
Definition: aes.c:53
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