55 #ifndef UDMA_CONF_MAX_CHANNEL 56 #define UDMA_CONF_MAX_CHANNEL 31 63 #define UDMA_STAT 0x400FF000 64 #define UDMA_CFG 0x400FF004 65 #define UDMA_CTLBASE 0x400FF008 66 #define UDMA_ALTBASE 0x400FF00C 67 #define UDMA_WAITSTAT 0x400FF010 68 #define UDMA_SWREQ 0x400FF014 69 #define UDMA_USEBURSTSET 0x400FF018 70 #define UDMA_USEBURSTCLR 0x400FF01C 71 #define UDMA_REQMASKSET 0x400FF020 72 #define UDMA_REQMASKCLR 0x400FF024 73 #define UDMA_ENASET 0x400FF028 74 #define UDMA_ENACLR 0x400FF02C 75 #define UDMA_ALTSET 0x400FF030 76 #define UDMA_ALTCLR 0x400FF034 77 #define UDMA_PRIOSET 0x400FF038 78 #define UDMA_PRIOCLR 0x400FF03C 79 #define UDMA_ERRCLR 0x400FF04C 80 #define UDMA_CHASGN 0x400FF500 81 #define UDMA_CHIS 0x400FF504 82 #define UDMA_CHMAP0 0x400FF510 83 #define UDMA_CHMAP1 0x400FF514 84 #define UDMA_CHMAP2 0x400FF518 85 #define UDMA_CHMAP3 0x400FF51C 92 #define UDMA_STAT_DMACHANS 0x001F0000 93 #define UDMA_STAT_STATE 0x000000F0 94 #define UDMA_STAT_MASTEN 0x00000001 101 #define UDMA_CFG_MASTEN 0x00000001 108 #define UDMA_CTLBASE_ADDR 0xFFFFFC00 115 #define UDMA_ALTBASE_ADDR 0xFFFFFFFF 122 #define UDMA_WAITSTAT_WAITREQ 0xFFFFFFFF 129 #define UDMA_SWREQ_SWREQ 0xFFFFFFFF 136 #define UDMA_USEBURSTSET_SET 0xFFFFFFFF 143 #define UDMA_USEBURSTCLR_CLR 0xFFFFFFFF 150 #define UDMA_REQMASKSET_SET 0xFFFFFFFF 157 #define UDMA_REQMASKCLR_CLR 0xFFFFFFFF 164 #define UDMA_ENASET_SET 0xFFFFFFFF 171 #define UDMA_ENACLR_CLR 0xFFFFFFFF 178 #define UDMA_ALTSET_SET 0xFFFFFFFF 185 #define UDMA_ALTCLR_CLR 0xFFFFFFFF 192 #define UDMA_PRIOSET_SET 0xFFFFFFFF 199 #define UDMA_PRIOCLR_CLR 0xFFFFFFFF 206 #define UDMA_ERRCLR_ERRCLR 0x00000001 213 #define UDMA_CHASGN_CHASGN 0xFFFFFFFF 220 #define UDMA_CHIS_CHIS 0xFFFFFFFF 227 #define UDMA_CHMAP0_CH7SEL 0xF0000000 228 #define UDMA_CHMAP0_CH6SEL 0x0F000000 229 #define UDMA_CHMAP0_CH5SEL 0x00F00000 230 #define UDMA_CHMAP0_CH4SEL 0x000F0000 231 #define UDMA_CHMAP0_CH3SEL 0x0000F000 232 #define UDMA_CHMAP0_CH2SEL 0x00000F00 233 #define UDMA_CHMAP0_CH1SEL 0x000000F0 234 #define UDMA_CHMAP0_CH0SEL 0x0000000F 240 #define UDMA_CHMAP1_CH15SEL 0xF0000000 241 #define UDMA_CHMAP1_CH14SEL 0x0F000000 242 #define UDMA_CHMAP1_CH13SEL 0x00F00000 243 #define UDMA_CHMAP1_CH12SEL 0x000F0000 244 #define UDMA_CHMAP1_CH11SEL 0x0000F000 245 #define UDMA_CHMAP1_CH10SEL 0x00000F00 246 #define UDMA_CHMAP1_CH9SEL 0x000000F0 247 #define UDMA_CHMAP1_CH8SEL 0x0000000F 254 #define UDMA_CHMAP2_CH23SEL 0xF0000000 255 #define UDMA_CHMAP2_CH22SEL 0x0F000000 256 #define UDMA_CHMAP2_CH21SEL 0x00F00000 257 #define UDMA_CHMAP2_CH20SEL 0x000F0000 258 #define UDMA_CHMAP2_CH19SEL 0x0000F000 259 #define UDMA_CHMAP2_CH18SEL 0x00000F00 260 #define UDMA_CHMAP2_CH17SEL 0x000000F0 261 #define UDMA_CHMAP2_CH16SEL 0x0000000F 268 #define UDMA_CHMAP3_CH31SEL 0xF0000000 269 #define UDMA_CHMAP3_CH30SEL 0x0F000000 270 #define UDMA_CHMAP3_CH29SEL 0x00F00000 271 #define UDMA_CHMAP3_CH28SEL 0x000F0000 272 #define UDMA_CHMAP3_CH27SEL 0x0000F000 273 #define UDMA_CHMAP3_CH26SEL 0x00000F00 274 #define UDMA_CHMAP3_CH25SEL 0x000000F0 275 #define UDMA_CHMAP3_CH24SEL 0x0000000F 283 #define UDMA_CH0_RESERVED0 0x00 284 #define UDMA_CH0_RESERVED1 0x01 285 #define UDMA_CH0_RESERVED2 0x02 286 #define UDMA_CH0_RESERVED3 0x03 287 #define UDMA_CH0_USB 0x04 290 #define UDMA_CH1_RESERVED0 0x00 291 #define UDMA_CH1_RESERVED1 0x01 292 #define UDMA_CH1_RESERVED2 0x02 293 #define UDMA_CH1_RESERVED3 0x03 294 #define UDMA_CH1_ADC 0x04 297 #define UDMA_CH2_RESERVED0 0x00 298 #define UDMA_CH2_TIMER3A 0x01 299 #define UDMA_CH2_RESERVED2 0x02 300 #define UDMA_CH2_RESERVED3 0x03 301 #define UDMA_CH2_FLASH 0x04 304 #define UDMA_CH3_RESERVED0 0x00 305 #define UDMA_CH3_TIMER3B 0x01 306 #define UDMA_CH3_RESERVED2 0x02 307 #define UDMA_CH3_RESERVED3 0x03 308 #define UDMA_CH3_RFCORETRG1 0x04 311 #define UDMA_CH4_RESERVED0 0x00 312 #define UDMA_CH4_TIMER2A 0x01 313 #define UDMA_CH4_RESERVED2 0x02 314 #define UDMA_CH4_RESERVED3 0x03 315 #define UDMA_CH4_RFCORETRG2 0x04 318 #define UDMA_CH5_RESERVED0 0x00 319 #define UDMA_CH5_TIMER2B 0x01 320 #define UDMA_CH5_RESERVED2 0x02 321 #define UDMA_CH5_RESERVED3 0x03 322 #define UDMA_CH5_RESERVED4 0x04 325 #define UDMA_CH6_RESERVED0 0x00 326 #define UDMA_CH6_TIMER2A 0x01 327 #define UDMA_CH6_RESERVED2 0x02 328 #define UDMA_CH6_RESERVED3 0x03 329 #define UDMA_CH6_RESERVED4 0x04 332 #define UDMA_CH7_RESERVED0 0x00 333 #define UDMA_CH7_TIMER2B 0x01 334 #define UDMA_CH7_RESERVED2 0x02 335 #define UDMA_CH7_RESERVED3 0x03 336 #define UDMA_CH7_RESERVED4 0x04 339 #define UDMA_CH8_UART0RX 0x00 340 #define UDMA_CH8_UART1RX 0x01 341 #define UDMA_CH8_RESERVED2 0x02 342 #define UDMA_CH8_RESERVED3 0x03 343 #define UDMA_CH8_RESERVED4 0x04 346 #define UDMA_CH9_UART0TX 0x00 347 #define UDMA_CH9_UART1TX 0x01 348 #define UDMA_CH9_RESERVED2 0x02 349 #define UDMA_CH9_RESERVED3 0x03 350 #define UDMA_CH9_RESERVED4 0x04 353 #define UDMA_CH10_SSI0RX 0x00 354 #define UDMA_CH10_SSI1RX 0x01 355 #define UDMA_CH10_RESERVED2 0x02 356 #define UDMA_CH10_RESERVED3 0x03 357 #define UDMA_CH10_RESERVED4 0x04 360 #define UDMA_CH11_SSI0TX 0x00 361 #define UDMA_CH11_SSI1TX 0x01 362 #define UDMA_CH11_RESERVED2 0x02 363 #define UDMA_CH11_RESERVED3 0x03 364 #define UDMA_CH11_RESERVED4 0x04 367 #define UDMA_CH12_RESERVED0 0x00 368 #define UDMA_CH12_RESERVED1 0x01 369 #define UDMA_CH12_RESERVED2 0x02 370 #define UDMA_CH12_RESERVED3 0x03 371 #define UDMA_CH12_RESERVED4 0x04 374 #define UDMA_CH13_RESERVED0 0x00 375 #define UDMA_CH13_RESERVED1 0x01 376 #define UDMA_CH13_RESERVED2 0x02 377 #define UDMA_CH13_RESERVED3 0x03 378 #define UDMA_CH13_RESERVED4 0x04 381 #define UDMA_CH14_ADC0 0x00 382 #define UDMA_CH14_TIMER2A 0x01 383 #define UDMA_CH14_RESERVED2 0x02 384 #define UDMA_CH14_RESERVED3 0x03 385 #define UDMA_CH14_RESERVED4 0x04 388 #define UDMA_CH15_ADC1 0x00 389 #define UDMA_CH15_TIMER2B 0x01 390 #define UDMA_CH15_RESERVED2 0x02 391 #define UDMA_CH15_RESERVED3 0x03 392 #define UDMA_CH15_RESERVED4 0x04 395 #define UDMA_CH16_ADC2 0x00 396 #define UDMA_CH16_RESERVED1 0x01 397 #define UDMA_CH16_RESERVED2 0x02 398 #define UDMA_CH16_RESERVED3 0x03 399 #define UDMA_CH16_RESERVED4 0x04 402 #define UDMA_CH17_ADC3 0x00 403 #define UDMA_CH17_RESERVED1 0x01 404 #define UDMA_CH17_RESERVED2 0x02 405 #define UDMA_CH17_RESERVED3 0x03 406 #define UDMA_CH17_RESERVED4 0x04 409 #define UDMA_CH18_TIMER0A 0x00 410 #define UDMA_CH18_TIMER1A 0x01 411 #define UDMA_CH18_RESERVED2 0x02 412 #define UDMA_CH18_RESERVED3 0x03 413 #define UDMA_CH18_RESERVED4 0x04 416 #define UDMA_CH19_TIMER0B 0x00 417 #define UDMA_CH19_TIMER1B 0x01 418 #define UDMA_CH19_RESERVED2 0x02 419 #define UDMA_CH19_RESERVED3 0x03 420 #define UDMA_CH19_RESERVED4 0x04 423 #define UDMA_CH20_TIMER1A 0x00 424 #define UDMA_CH20_RESERVED1 0x01 425 #define UDMA_CH20_RESERVED2 0x02 426 #define UDMA_CH20_RESERVED3 0x03 427 #define UDMA_CH20_RESERVED4 0x04 430 #define UDMA_CH21_TIMER1B 0x00 431 #define UDMA_CH21_RESERVED1 0x01 432 #define UDMA_CH21_RESERVED2 0x02 433 #define UDMA_CH21_RESERVED3 0x03 434 #define UDMA_CH21_RESERVED4 0x04 437 #define UDMA_CH22_UART1RX 0x00 438 #define UDMA_CH22_RESERVED1 0x01 439 #define UDMA_CH22_RESERVED2 0x02 440 #define UDMA_CH22_RESERVED3 0x03 441 #define UDMA_CH22_RESERVED4 0x04 444 #define UDMA_CH23_UART1TX 0x00 445 #define UDMA_CH23_RESERVED1 0x01 446 #define UDMA_CH23_RESERVED2 0x02 447 #define UDMA_CH23_RESERVED3 0x03 448 #define UDMA_CH23_RESERVED4 0x04 451 #define UDMA_CH24_SSI1RX 0x00 452 #define UDMA_CH24_ADC4 0x01 453 #define UDMA_CH24_RESERVED2 0x02 454 #define UDMA_CH24_RESERVED3 0x03 455 #define UDMA_CH24_RESERVED4 0x04 458 #define UDMA_CH25_SSI1TX 0x00 459 #define UDMA_CH25_ADC5 0x01 460 #define UDMA_CH25_RESERVED2 0x02 461 #define UDMA_CH25_RESERVED3 0x03 462 #define UDMA_CH25_RESERVED4 0x04 465 #define UDMA_CH26_RESERVED0 0x00 466 #define UDMA_CH26_ADC6 0x01 467 #define UDMA_CH26_RESERVED2 0x02 468 #define UDMA_CH26_RESERVED3 0x03 469 #define UDMA_CH26_RESERVED4 0x04 472 #define UDMA_CH27_RESERVED0 0x00 473 #define UDMA_CH27_ADC7 0x01 474 #define UDMA_CH27_RESERVED2 0x02 475 #define UDMA_CH27_RESERVED3 0x03 476 #define UDMA_CH27_RESERVED4 0x04 479 #define UDMA_CH28_RESERVED0 0x00 480 #define UDMA_CH28_RESERVED1 0x01 481 #define UDMA_CH28_RESERVED2 0x02 482 #define UDMA_CH28_RESERVED3 0x03 483 #define UDMA_CH28_RESERVED4 0x04 486 #define UDMA_CH29_RESERVED0 0x00 487 #define UDMA_CH29_RESERVED1 0x01 488 #define UDMA_CH29_RESERVED2 0x02 489 #define UDMA_CH29_RESERVED3 0x03 490 #define UDMA_CH29_RFCORET2TRG1 0x04 493 #define UDMA_CH30_SW 0x00 494 #define UDMA_CH30_RESERVED1 0x01 495 #define UDMA_CH30_RESERVED2 0x02 496 #define UDMA_CH30_RESERVED3 0x03 497 #define UDMA_CH30_RFCORET2TRG2 0x04 500 #define UDMA_CH31_RESERVED0 0x00 501 #define UDMA_CH31_RESERVED1 0x01 502 #define UDMA_CH31_RESERVED2 0x02 503 #define UDMA_CH31_RESERVED3 0x03 504 #define UDMA_CH31_RESERVED4 0x04 512 #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 513 #define UDMA_CHCTL_DSTINC_32 0x80000000 514 #define UDMA_CHCTL_DSTINC_16 0x40000000 515 #define UDMA_CHCTL_DSTINC_8 0x00000000 517 #define UDMA_CHCTL_DSTSIZE_32 0x20000000 518 #define UDMA_CHCTL_DSTSIZE_16 0x10000000 519 #define UDMA_CHCTL_DSTSIZE_8 0x00000000 521 #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 522 #define UDMA_CHCTL_SRCINC_32 0x08000000 523 #define UDMA_CHCTL_SRCINC_16 0x04000000 524 #define UDMA_CHCTL_SRCINC_8 0x00000000 526 #define UDMA_CHCTL_SRCSIZE_32 0x02000000 527 #define UDMA_CHCTL_SRCSIZE_16 0x01000000 528 #define UDMA_CHCTL_SRCSIZE_8 0x00000000 530 #define UDMA_CHCTL_ARBSIZE_1 0x00000000 531 #define UDMA_CHCTL_ARBSIZE_2 0x00004000 532 #define UDMA_CHCTL_ARBSIZE_4 0x00008000 533 #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 534 #define UDMA_CHCTL_ARBSIZE_16 0x00010000 535 #define UDMA_CHCTL_ARBSIZE_32 0x00014000 536 #define UDMA_CHCTL_ARBSIZE_64 0x00018000 537 #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 538 #define UDMA_CHCTL_ARBSIZE_256 0x00020000 539 #define UDMA_CHCTL_ARBSIZE_512 0x00024000 540 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 542 #define UDMA_CHCTL_XFERMODE_STOP 0x00000000 543 #define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 544 #define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 545 #define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 546 #define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 547 #define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 548 #define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 549 #define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 697 #define udma_xfer_size(len) ((len - 1) << 4) void udma_channel_mask_clr(uint8_t channel)
Enable peripheral triggers for a uDMA channel.
void udma_set_channel_dst(uint8_t channel, uint32_t dst_end)
Sets the channel's destination address.
void udma_channel_use_alternate(uint8_t channel)
Use the alternate control data structure for a channel.
void udma_channel_use_primary(uint8_t channel)
Use the primary control data structure for a channel.
void udma_channel_prio_set_high(uint8_t channel)
Set a uDMA channel to high priority.
void udma_channel_mask_set(uint8_t channel)
Disable peripheral triggers for a uDMA channel.
void udma_set_channel_src(uint8_t channel, uint32_t src_end)
Sets the channels source address.
void udma_channel_enable(uint8_t channel)
Enables a uDMA channel.
void udma_set_channel_assignment(uint8_t channel, uint8_t enc)
Choose an encoding for a uDMA channel.
void udma_channel_sw_request(uint8_t channel)
Generate a software trigger to start a transfer.
void udma_channel_disable(uint8_t channel)
Disables a uDMA channel.
void udma_channel_use_burst(uint8_t channel)
Configure a channel to only use burst transfers.
void udma_init()
Initialise the uDMA driver.
void udma_channel_prio_set_default(uint8_t channel)
Set a uDMA channel to default priority.
void udma_set_channel_control_word(uint8_t channel, uint32_t ctrl)
Configure the channel's control word.
uint8_t udma_channel_get_mode(uint8_t channel)
Retrieve the current mode for a channel.
void udma_channel_use_single(uint8_t channel)
Configure a channel to use single as well as burst requests.