Go to the documentation of this file. 48 #define RADIO_PHY_OVERHEAD 3 50 #define RADIO_BYTE_AIR_TIME 32 53 #define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456)) 56 #define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183)) 58 #define RADIO_DELAY_BEFORE_DETECT 0 61 #define TSCH_CONF_HW_FRAME_FILTERING 0 63 #define PLATFORM_HAS_LEDS 1 64 #define PLATFORM_HAS_BUTTON 1 65 #define PLATFORM_HAS_LIGHT 1 66 #define PLATFORM_HAS_BATTERY 1 67 #define PLATFORM_HAS_SHT11 1 68 #define PLATFORM_HAS_RADIO 1 71 #define F_CPU 3900000uL 74 #define NETSTACK_CONF_RADIO cc2420_driver 77 #define LEDS_PxDIR P5DIR 78 #define LEDS_PxOUT P5OUT 79 #define LEDS_CONF_RED 0x10 80 #define LEDS_CONF_GREEN 0x20 81 #define LEDS_CONF_YELLOW 0x40 83 #define LEDS_CONF_LEGACY_API 1 86 #ifndef DCOSYNCH_CONF_ENABLED 87 #define DCOSYNCH_CONF_ENABLED (!(MAC_CONF_WITH_TSCH)) 91 #ifndef CC2420_CONF_SFD_TIMESTAMPS 92 #define CC2420_CONF_SFD_TIMESTAMPS (MAC_CONF_WITH_TSCH) 95 #ifndef DCOSYNCH_CONF_PERIOD 96 #define DCOSYNCH_CONF_PERIOD 30 99 #define ROM_ERASE_UNIT_SIZE 512 100 #define XMEM_ERASE_UNIT_SIZE (64*1024L) 103 #define CFS_CONF_OFFSET_TYPE long 107 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE) 110 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE) 112 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE) 113 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE) 115 #define CFS_RAM_CONF_SIZE 4096 122 #define SPI_TXBUF U0TXBUF 123 #define SPI_RXBUF U0RXBUF 126 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0) 128 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0) 130 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0) 146 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) ) 147 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) ) 149 #define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) ) 150 #define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) ) 156 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800 159 #define CC2420_FIFOP_PORT(type) P1##type 160 #define CC2420_FIFOP_PIN 0 162 #define CC2420_FIFO_PORT(type) P1##type 163 #define CC2420_FIFO_PIN 3 165 #define CC2420_CCA_PORT(type) P1##type 166 #define CC2420_CCA_PIN 4 168 #define CC2420_SFD_PORT(type) P4##type 169 #define CC2420_SFD_PIN 1 171 #define CC2420_CSN_PORT(type) P4##type 172 #define CC2420_CSN_PIN 2 174 #define CC2420_VREG_PORT(type) P4##type 175 #define CC2420_VREG_PIN 5 177 #define CC2420_RESET_PORT(type) P4##type 178 #define CC2420_RESET_PIN 6 180 #define CC2420_IRQ_VECTOR PORT1_VECTOR 183 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN))) 184 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN))) 185 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN))) 186 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN))) 189 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN)) 190 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN)) 193 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN)) 194 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN)) 197 #define CC2420_FIFOP_INT_INIT() do { \ 198 CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \ 199 CC2420_CLEAR_FIFOP_INT(); \ 203 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0) 204 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0) 205 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0) 213 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN)) 215 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN)) 216 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN)) 219 #define STACK_CONF_ORIGIN ((void *)0x3900)