1 #ifndef USB_ARCH_H_0Z52ZDP0H6__ 2 #define USB_ARCH_H_0Z52ZDP0H6__ 9 #ifndef USB_MAX_ENDPOINTS 10 #define USB_MAX_ENDPOINTS 4 14 #define CTRL_EP_SIZE 8 18 #define USB_EP1_SIZE 8 21 #define USB_EP2_SIZE 8 24 #define USB_EP3_SIZE 8 27 #define USB_EP4_SIZE 0 30 #define USB_EP5_SIZE 0 33 #define USB_EP6_SIZE 0 36 #define USB_EP7_SIZE 0 41 #define MAX_CTRL_DATA 128 44 void usb_arch_setup(
void);
46 void usb_arch_setup_control_endpoint(uint8_t
addr);
48 void usb_arch_setup_bulk_endpoint(uint8_t
addr);
50 void usb_arch_setup_interrupt_endpoint(uint8_t
addr);
52 void usb_arch_disable_endpoint(uint8_t
addr);
54 void usb_arch_discard_all_buffers(uint8_t
addr);
58 void usb_arch_control_stall(uint8_t
addr);
61 void usb_arch_halt_endpoint(uint8_t
addr,
int halt);
63 void usb_arch_set_configuration(uint8_t usb_configuration_value);
65 uint16_t usb_arch_get_ep_status(uint8_t
addr);
67 void usb_arch_set_address(uint8_t
addr);
70 void usb_arch_set_global_event_process(
struct process *p);
72 unsigned int usb_arch_get_global_events(
void);
75 int usb_arch_send_pending(uint8_t ep_addr);
static uip_ds6_addr_t * addr
Pointer to a nbr cache entry.