Contiki-NG
udma.h
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1/*
2 * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * 3. Neither the name of the copyright holder nor the names of its
15 * contributors may be used to endorse or promote products derived
16 * from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29 * OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31/**
32 * \addtogroup cc2538
33 * @{
34 *
35 * \defgroup cc2538-udma cc2538 micro-DMA
36 *
37 * Driver for the cc2538 uDMA controller
38 * @{
39 *
40 * \file
41 * Header file with register, macro and function declarations for the cc2538
42 * micro-DMA controller module
43 */
44#ifndef UDMA_H_
45#define UDMA_H_
46
47#include "contiki.h"
48
49/*
50 * Enable all uDMA channels unless a conf file tells us to do otherwise.
51 * Using all 31 channels will consume a lot of RAM for the channel control
52 * data structure. Thus it's wise to set this define to the number of the
53 * highest channel in use
54 */
55#ifndef UDMA_CONF_MAX_CHANNEL
56#define UDMA_CONF_MAX_CHANNEL 31
57#endif
58/*---------------------------------------------------------------------------*/
59/**
60 * \name uDMA Register offset declarations
61 * @{
62 */
63#define UDMA_STAT 0x400FF000 /**< DMA status */
64#define UDMA_CFG 0x400FF004 /**< DMA configuration */
65#define UDMA_CTLBASE 0x400FF008 /**< DMA channel control base pointer */
66#define UDMA_ALTBASE 0x400FF00C /**< DMA alternate channel control base pointer */
67#define UDMA_WAITSTAT 0x400FF010 /**< DMA channel wait-on-request status */
68#define UDMA_SWREQ 0x400FF014 /**< DMA channel software request */
69#define UDMA_USEBURSTSET 0x400FF018 /**< DMA channel useburst set */
70#define UDMA_USEBURSTCLR 0x400FF01C /**< DMA channel useburst clear */
71#define UDMA_REQMASKSET 0x400FF020 /**< DMA channel request mask set */
72#define UDMA_REQMASKCLR 0x400FF024 /**< DMA channel request mask clear */
73#define UDMA_ENASET 0x400FF028 /**< DMA channel enable set */
74#define UDMA_ENACLR 0x400FF02C /**< DMA channel enable clear */
75#define UDMA_ALTSET 0x400FF030 /**< DMA channel primary alternate set */
76#define UDMA_ALTCLR 0x400FF034 /**< DMA channel primary alternate clear */
77#define UDMA_PRIOSET 0x400FF038 /**< DMA channel priority set */
78#define UDMA_PRIOCLR 0x400FF03C /**< DMA channel priority clear */
79#define UDMA_ERRCLR 0x400FF04C /**< DMA bus error clear */
80#define UDMA_CHASGN 0x400FF500 /**< DMA channel assignment */
81#define UDMA_CHIS 0x400FF504 /**< DMA channel interrupt status */
82#define UDMA_CHMAP0 0x400FF510 /**< DMA channel map select 0 */
83#define UDMA_CHMAP1 0x400FF514 /**< DMA channel map select 1 */
84#define UDMA_CHMAP2 0x400FF518 /**< DMA channel map select 2 */
85#define UDMA_CHMAP3 0x400FF51C /**< DMA channel map select 3 */
86/** @} */
87/*---------------------------------------------------------------------------*/
88/**
89 * \name UDMA_STAT register bit masks
90 * @{
91 */
92#define UDMA_STAT_DMACHANS 0x001F0000 /**< Available uDMA channels minus 1 */
93#define UDMA_STAT_STATE 0x000000F0 /**< Control state machine status */
94#define UDMA_STAT_MASTEN 0x00000001 /**< Master enable status */
95/** @} */
96/*---------------------------------------------------------------------------*/
97/**
98 * \name UDMA_CFG register bit masks
99 * @{
100 */
101#define UDMA_CFG_MASTEN 0x00000001 /**< Controller master enable */
102/** @} */
103/*---------------------------------------------------------------------------*/
104/**
105 * \name UDMA_CTLBASE register bit masks
106 * @{
107 */
108#define UDMA_CTLBASE_ADDR 0xFFFFFC00 /**< Channel control base address */
109/** @} */
110/*---------------------------------------------------------------------------*/
111/**
112 * \name UDMA_ALTBASE register bit masks
113 * @{
114 */
115#define UDMA_ALTBASE_ADDR 0xFFFFFFFF /**< Alternate channel address pointer */
116/** @} */
117/*---------------------------------------------------------------------------*/
118/**
119 * \name UDMA_WAITSTAT register bit masks
120 * @{
121 */
122#define UDMA_WAITSTAT_WAITREQ 0xFFFFFFFF /**< Channel [n] wait status */
123/** @} */
124/*---------------------------------------------------------------------------*/
125/**
126 * \name UDMA_SWREQ register bit masks
127 * @{
128 */
129#define UDMA_SWREQ_SWREQ 0xFFFFFFFF /**< Channel [n] software request */
130/** @} */
131/*---------------------------------------------------------------------------*/
132/**
133 * \name UDMA_USEBURSTSET register bit masks
134 * @{
135 */
136#define UDMA_USEBURSTSET_SET 0xFFFFFFFF /**< Channel [n] useburst set */
137/** @} */
138/*---------------------------------------------------------------------------*/
139/**
140 * \name UDMA_USEBURSTCLR register bit masks
141 * @{
142 */
143#define UDMA_USEBURSTCLR_CLR 0xFFFFFFFF /**< Channel [n] useburst clear */
144/** @} */
145/*---------------------------------------------------------------------------*/
146/**
147 * \name UDMA_REQMASKSET register bit masks
148 * @{
149 */
150#define UDMA_REQMASKSET_SET 0xFFFFFFFF /**< Channel [n] request mask set */
151/** @} */
152/*---------------------------------------------------------------------------*/
153/**
154 * \name UDMA_REQMASKCLR register bit masks
155 * @{
156 */
157#define UDMA_REQMASKCLR_CLR 0xFFFFFFFF /**< Channel [n] request mask clear */
158/** @} */
159/*---------------------------------------------------------------------------*/
160/**
161 * \name UDMA_ENASET register bit masks
162 * @{
163 */
164#define UDMA_ENASET_SET 0xFFFFFFFF /**< Channel [n] enable set */
165/** @} */
166/*---------------------------------------------------------------------------*/
167/**
168 * \name UDMA_ENACLR register bit masks
169 * @{
170 */
171#define UDMA_ENACLR_CLR 0xFFFFFFFF /**< Channel [n] enable clear */
172/** @} */
173/*---------------------------------------------------------------------------*/
174/**
175 * \name UDMA_ALTSET register bit masks
176 * @{
177 */
178#define UDMA_ALTSET_SET 0xFFFFFFFF /**< Channel [n] alternate set */
179/** @} */
180/*---------------------------------------------------------------------------*/
181/**
182 * \name UDMA_ALTCLR register bit masks
183 * @{
184 */
185#define UDMA_ALTCLR_CLR 0xFFFFFFFF /**< Channel [n] alternate clear */
186/** @} */
187/*---------------------------------------------------------------------------*/
188/**
189 * \name UDMA_PRIOSET register bit masks
190 * @{
191 */
192#define UDMA_PRIOSET_SET 0xFFFFFFFF /**< Channel [n] priority set */
193/** @} */
194/*---------------------------------------------------------------------------*/
195/**
196 * \name UDMA_PRIOCLR register bit masks
197 * @{
198 */
199#define UDMA_PRIOCLR_CLR 0xFFFFFFFF /**< Channel [n] priority clear */
200/** @} */
201/*---------------------------------------------------------------------------*/
202/**
203 * \name UDMA_ERRCLR register bit masks
204 * @{
205 */
206#define UDMA_ERRCLR_ERRCLR 0x00000001 /**< uDMA bus error status */
207/** @} */
208/*---------------------------------------------------------------------------*/
209/**
210 * \name UDMA_CHASGN register bit masks
211 * @{
212 */
213#define UDMA_CHASGN_CHASGN 0xFFFFFFFF /**< Channel [n] assignment select */
214/** @} */
215/*---------------------------------------------------------------------------*/
216/**
217 * \name UDMA_CHIS register bit masks
218 * @{
219 */
220#define UDMA_CHIS_CHIS 0xFFFFFFFF /**< Channel [n] interrupt status */
221/** @} */
222/*---------------------------------------------------------------------------*/
223/**
224 * \name UDMA_CHMAP0 register bit masks
225 * @{
226 */
227#define UDMA_CHMAP0_CH7SEL 0xF0000000 /**< uDMA channel 7 source select */
228#define UDMA_CHMAP0_CH6SEL 0x0F000000 /**< uDMA channel 6 source select */
229#define UDMA_CHMAP0_CH5SEL 0x00F00000 /**< uDMA channel 5 source select */
230#define UDMA_CHMAP0_CH4SEL 0x000F0000 /**< uDMA channel 4 source select */
231#define UDMA_CHMAP0_CH3SEL 0x0000F000 /**< uDMA channel 3 source select */
232#define UDMA_CHMAP0_CH2SEL 0x00000F00 /**< uDMA channel 2 source select */
233#define UDMA_CHMAP0_CH1SEL 0x000000F0 /**< uDMA channel 1 source select */
234#define UDMA_CHMAP0_CH0SEL 0x0000000F /**< uDMA channel 0 source select */
235/** @} */
236/*---------------------------------------------------------------------------*/
237/** \name UDMA_CHMAP1 register bit masks
238 * @{
239 */
240#define UDMA_CHMAP1_CH15SEL 0xF0000000 /**< uDMA channel 15 source select */
241#define UDMA_CHMAP1_CH14SEL 0x0F000000 /**< uDMA channel 14 source select */
242#define UDMA_CHMAP1_CH13SEL 0x00F00000 /**< uDMA channel 13 source select */
243#define UDMA_CHMAP1_CH12SEL 0x000F0000 /**< uDMA channel 12 source select */
244#define UDMA_CHMAP1_CH11SEL 0x0000F000 /**< uDMA channel 11 source select */
245#define UDMA_CHMAP1_CH10SEL 0x00000F00 /**< uDMA channel 10 source select */
246#define UDMA_CHMAP1_CH9SEL 0x000000F0 /**< uDMA channel 9 source select */
247#define UDMA_CHMAP1_CH8SEL 0x0000000F /**< uDMA channel 8 source select */
248/** @} */
249/*---------------------------------------------------------------------------*/
250/**
251 * \name UDMA_CHMAP2 register bit masks
252 * @{
253 */
254#define UDMA_CHMAP2_CH23SEL 0xF0000000 /**< uDMA channel 23 source select */
255#define UDMA_CHMAP2_CH22SEL 0x0F000000 /**< uDMA channel 22 source select */
256#define UDMA_CHMAP2_CH21SEL 0x00F00000 /**< uDMA channel 21 source select */
257#define UDMA_CHMAP2_CH20SEL 0x000F0000 /**< uDMA channel 20 source select */
258#define UDMA_CHMAP2_CH19SEL 0x0000F000 /**< uDMA channel 19 source select */
259#define UDMA_CHMAP2_CH18SEL 0x00000F00 /**< uDMA channel 18 source select */
260#define UDMA_CHMAP2_CH17SEL 0x000000F0 /**< uDMA channel 17 source select */
261#define UDMA_CHMAP2_CH16SEL 0x0000000F /**< uDMA channel 16 source select */
262/** @} */
263/*---------------------------------------------------------------------------*/
264/**
265 * \name UDMA_CHMAP3 register bit masks
266 * @{
267 */
268#define UDMA_CHMAP3_CH31SEL 0xF0000000 /**< uDMA channel 31 source select */
269#define UDMA_CHMAP3_CH30SEL 0x0F000000 /**< uDMA channel 30 source select */
270#define UDMA_CHMAP3_CH29SEL 0x00F00000 /**< uDMA channel 29 source select */
271#define UDMA_CHMAP3_CH28SEL 0x000F0000 /**< uDMA channel 28 source select */
272#define UDMA_CHMAP3_CH27SEL 0x0000F000 /**< uDMA channel 27 source select */
273#define UDMA_CHMAP3_CH26SEL 0x00000F00 /**< uDMA channel 26 source select */
274#define UDMA_CHMAP3_CH25SEL 0x000000F0 /**< uDMA channel 25 source select */
275#define UDMA_CHMAP3_CH24SEL 0x0000000F /**< uDMA channel 24 source select */
276/** @} */
277/*---------------------------------------------------------------------------*/
278/**
279 * \name uDMA Channel encoding assignments
280 * @{
281 */
282/* Channel 0 */
283#define UDMA_CH0_RESERVED0 0x00
284#define UDMA_CH0_RESERVED1 0x01
285#define UDMA_CH0_RESERVED2 0x02
286#define UDMA_CH0_RESERVED3 0x03
287#define UDMA_CH0_USB 0x04
288
289/* Channel 1 */
290#define UDMA_CH1_RESERVED0 0x00
291#define UDMA_CH1_RESERVED1 0x01
292#define UDMA_CH1_RESERVED2 0x02
293#define UDMA_CH1_RESERVED3 0x03
294#define UDMA_CH1_ADC 0x04
295
296/* Channel 2 */
297#define UDMA_CH2_RESERVED0 0x00
298#define UDMA_CH2_TIMER3A 0x01
299#define UDMA_CH2_RESERVED2 0x02
300#define UDMA_CH2_RESERVED3 0x03
301#define UDMA_CH2_FLASH 0x04
302
303/* Channel 3 */
304#define UDMA_CH3_RESERVED0 0x00
305#define UDMA_CH3_TIMER3B 0x01
306#define UDMA_CH3_RESERVED2 0x02
307#define UDMA_CH3_RESERVED3 0x03
308#define UDMA_CH3_RFCORETRG1 0x04
309
310/* Channel 4 */
311#define UDMA_CH4_RESERVED0 0x00
312#define UDMA_CH4_TIMER2A 0x01
313#define UDMA_CH4_RESERVED2 0x02
314#define UDMA_CH4_RESERVED3 0x03
315#define UDMA_CH4_RFCORETRG2 0x04
316
317/* Channel 5 */
318#define UDMA_CH5_RESERVED0 0x00
319#define UDMA_CH5_TIMER2B 0x01
320#define UDMA_CH5_RESERVED2 0x02
321#define UDMA_CH5_RESERVED3 0x03
322#define UDMA_CH5_RESERVED4 0x04
323
324/* Channel 6 */
325#define UDMA_CH6_RESERVED0 0x00
326#define UDMA_CH6_TIMER2A 0x01
327#define UDMA_CH6_RESERVED2 0x02
328#define UDMA_CH6_RESERVED3 0x03
329#define UDMA_CH6_RESERVED4 0x04
330
331/* Channel 7 */
332#define UDMA_CH7_RESERVED0 0x00
333#define UDMA_CH7_TIMER2B 0x01
334#define UDMA_CH7_RESERVED2 0x02
335#define UDMA_CH7_RESERVED3 0x03
336#define UDMA_CH7_RESERVED4 0x04
337
338/* Channel 8 */
339#define UDMA_CH8_UART0RX 0x00
340#define UDMA_CH8_UART1RX 0x01
341#define UDMA_CH8_RESERVED2 0x02
342#define UDMA_CH8_RESERVED3 0x03
343#define UDMA_CH8_RESERVED4 0x04
344
345/* Channel 9 */
346#define UDMA_CH9_UART0TX 0x00
347#define UDMA_CH9_UART1TX 0x01
348#define UDMA_CH9_RESERVED2 0x02
349#define UDMA_CH9_RESERVED3 0x03
350#define UDMA_CH9_RESERVED4 0x04
351
352/* Channel 10 */
353#define UDMA_CH10_SSI0RX 0x00
354#define UDMA_CH10_SSI1RX 0x01
355#define UDMA_CH10_RESERVED2 0x02
356#define UDMA_CH10_RESERVED3 0x03
357#define UDMA_CH10_RESERVED4 0x04
358
359/* Channel 11 */
360#define UDMA_CH11_SSI0TX 0x00
361#define UDMA_CH11_SSI1TX 0x01
362#define UDMA_CH11_RESERVED2 0x02
363#define UDMA_CH11_RESERVED3 0x03
364#define UDMA_CH11_RESERVED4 0x04
365
366/* Channel 12 */
367#define UDMA_CH12_RESERVED0 0x00
368#define UDMA_CH12_RESERVED1 0x01
369#define UDMA_CH12_RESERVED2 0x02
370#define UDMA_CH12_RESERVED3 0x03
371#define UDMA_CH12_RESERVED4 0x04
372
373/* Channel 13 */
374#define UDMA_CH13_RESERVED0 0x00
375#define UDMA_CH13_RESERVED1 0x01
376#define UDMA_CH13_RESERVED2 0x02
377#define UDMA_CH13_RESERVED3 0x03
378#define UDMA_CH13_RESERVED4 0x04
379
380/* Channel 14 */
381#define UDMA_CH14_ADC0 0x00
382#define UDMA_CH14_TIMER2A 0x01
383#define UDMA_CH14_RESERVED2 0x02
384#define UDMA_CH14_RESERVED3 0x03
385#define UDMA_CH14_RESERVED4 0x04
386
387/* Channel 15 */
388#define UDMA_CH15_ADC1 0x00
389#define UDMA_CH15_TIMER2B 0x01
390#define UDMA_CH15_RESERVED2 0x02
391#define UDMA_CH15_RESERVED3 0x03
392#define UDMA_CH15_RESERVED4 0x04
393
394/* Channel 16 */
395#define UDMA_CH16_ADC2 0x00
396#define UDMA_CH16_RESERVED1 0x01
397#define UDMA_CH16_RESERVED2 0x02
398#define UDMA_CH16_RESERVED3 0x03
399#define UDMA_CH16_RESERVED4 0x04
400
401/* Channel 17 */
402#define UDMA_CH17_ADC3 0x00
403#define UDMA_CH17_RESERVED1 0x01
404#define UDMA_CH17_RESERVED2 0x02
405#define UDMA_CH17_RESERVED3 0x03
406#define UDMA_CH17_RESERVED4 0x04
407
408/* Channel 18 */
409#define UDMA_CH18_TIMER0A 0x00
410#define UDMA_CH18_TIMER1A 0x01
411#define UDMA_CH18_RESERVED2 0x02
412#define UDMA_CH18_RESERVED3 0x03
413#define UDMA_CH18_RESERVED4 0x04
414
415/* Channel 19 */
416#define UDMA_CH19_TIMER0B 0x00
417#define UDMA_CH19_TIMER1B 0x01
418#define UDMA_CH19_RESERVED2 0x02
419#define UDMA_CH19_RESERVED3 0x03
420#define UDMA_CH19_RESERVED4 0x04
421
422/* Channel 20 */
423#define UDMA_CH20_TIMER1A 0x00
424#define UDMA_CH20_RESERVED1 0x01
425#define UDMA_CH20_RESERVED2 0x02
426#define UDMA_CH20_RESERVED3 0x03
427#define UDMA_CH20_RESERVED4 0x04
428
429/* Channel 21 */
430#define UDMA_CH21_TIMER1B 0x00
431#define UDMA_CH21_RESERVED1 0x01
432#define UDMA_CH21_RESERVED2 0x02
433#define UDMA_CH21_RESERVED3 0x03
434#define UDMA_CH21_RESERVED4 0x04
435
436/* Channel 22 */
437#define UDMA_CH22_UART1RX 0x00
438#define UDMA_CH22_RESERVED1 0x01
439#define UDMA_CH22_RESERVED2 0x02
440#define UDMA_CH22_RESERVED3 0x03
441#define UDMA_CH22_RESERVED4 0x04
442
443/* Channel 23 */
444#define UDMA_CH23_UART1TX 0x00
445#define UDMA_CH23_RESERVED1 0x01
446#define UDMA_CH23_RESERVED2 0x02
447#define UDMA_CH23_RESERVED3 0x03
448#define UDMA_CH23_RESERVED4 0x04
449
450/* Channel 24 */
451#define UDMA_CH24_SSI1RX 0x00
452#define UDMA_CH24_ADC4 0x01
453#define UDMA_CH24_RESERVED2 0x02
454#define UDMA_CH24_RESERVED3 0x03
455#define UDMA_CH24_RESERVED4 0x04
456
457/* Channel 25 */
458#define UDMA_CH25_SSI1TX 0x00
459#define UDMA_CH25_ADC5 0x01
460#define UDMA_CH25_RESERVED2 0x02
461#define UDMA_CH25_RESERVED3 0x03
462#define UDMA_CH25_RESERVED4 0x04
463
464/* Channel 26 */
465#define UDMA_CH26_RESERVED0 0x00
466#define UDMA_CH26_ADC6 0x01
467#define UDMA_CH26_RESERVED2 0x02
468#define UDMA_CH26_RESERVED3 0x03
469#define UDMA_CH26_RESERVED4 0x04
470
471/* Channel 27 */
472#define UDMA_CH27_RESERVED0 0x00
473#define UDMA_CH27_ADC7 0x01
474#define UDMA_CH27_RESERVED2 0x02
475#define UDMA_CH27_RESERVED3 0x03
476#define UDMA_CH27_RESERVED4 0x04
477
478/* Channel 28 */
479#define UDMA_CH28_RESERVED0 0x00
480#define UDMA_CH28_RESERVED1 0x01
481#define UDMA_CH28_RESERVED2 0x02
482#define UDMA_CH28_RESERVED3 0x03
483#define UDMA_CH28_RESERVED4 0x04
484
485/* Channel 29 */
486#define UDMA_CH29_RESERVED0 0x00
487#define UDMA_CH29_RESERVED1 0x01
488#define UDMA_CH29_RESERVED2 0x02
489#define UDMA_CH29_RESERVED3 0x03
490#define UDMA_CH29_RFCORET2TRG1 0x04
491
492/* Channel 30 */
493#define UDMA_CH30_SW 0x00
494#define UDMA_CH30_RESERVED1 0x01
495#define UDMA_CH30_RESERVED2 0x02
496#define UDMA_CH30_RESERVED3 0x03
497#define UDMA_CH30_RFCORET2TRG2 0x04
498
499/* Channel 31 */
500#define UDMA_CH31_RESERVED0 0x00
501#define UDMA_CH31_RESERVED1 0x01
502#define UDMA_CH31_RESERVED2 0x02
503#define UDMA_CH31_RESERVED3 0x03
504#define UDMA_CH31_RESERVED4 0x04
505/** @} */
506/*---------------------------------------------------------------------------*/
507/**
508 * \name Values to ORd together as the ctrl argument of
509 * udma_set_channel_control_word()
510 * @{
511 */
512#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 /**< Dst address no increment */
513#define UDMA_CHCTL_DSTINC_32 0x80000000 /**< Dst address increment 32 bit */
514#define UDMA_CHCTL_DSTINC_16 0x40000000 /**< Dst address increment 16 bit */
515#define UDMA_CHCTL_DSTINC_8 0x00000000 /**< Dst address increment 8 bit */
516
517#define UDMA_CHCTL_DSTSIZE_32 0x20000000 /**< Destination size 32 bit */
518#define UDMA_CHCTL_DSTSIZE_16 0x10000000 /**< Destination size 16 bit */
519#define UDMA_CHCTL_DSTSIZE_8 0x00000000 /**< Destination size 8 bit */
520
521#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 /**< Source address no increment */
522#define UDMA_CHCTL_SRCINC_32 0x08000000 /**< Source address increment 32 bit */
523#define UDMA_CHCTL_SRCINC_16 0x04000000 /**< Source address increment 16 bit */
524#define UDMA_CHCTL_SRCINC_8 0x00000000 /**< Source address increment 8 bit */
525
526#define UDMA_CHCTL_SRCSIZE_32 0x02000000 /**< Source size 32 bit */
527#define UDMA_CHCTL_SRCSIZE_16 0x01000000 /**< Source size 16 bit */
528#define UDMA_CHCTL_SRCSIZE_8 0x00000000 /**< Source size 8 bit */
529
530#define UDMA_CHCTL_ARBSIZE_1 0x00000000 /**< Arbitration size 1 Transfer */
531#define UDMA_CHCTL_ARBSIZE_2 0x00004000 /**< Arbitration size 2 Transfers */
532#define UDMA_CHCTL_ARBSIZE_4 0x00008000 /**< Arbitration size 4 Transfers */
533#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 /**< Arbitration size 8 Transfers */
534#define UDMA_CHCTL_ARBSIZE_16 0x00010000 /**< Arbitration size 16 Transfers */
535#define UDMA_CHCTL_ARBSIZE_32 0x00014000 /**< Arbitration size 32 Transfers */
536#define UDMA_CHCTL_ARBSIZE_64 0x00018000 /**< Arbitration size 64 Transfers */
537#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 /**< Arbitration size 128 Transfers */
538#define UDMA_CHCTL_ARBSIZE_256 0x00020000 /**< Arbitration size 256 Transfers */
539#define UDMA_CHCTL_ARBSIZE_512 0x00024000 /**< Arbitration size 512 Transfers */
540#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 /**< Arbitration size 1024 Transfers */
541
542#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 /**< Stop */
543#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 /**< Basic */
544#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 /**< Auto-Request */
545#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 /**< Ping-Pong */
546#define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 /**< Memory Scatter-Gather */
547#define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 /**< Memory Scatter-Gather Alt */
548#define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 /**< Peripheral Scatter-Gather */
549#define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 /**< Peripheral Scatter-Gather Alt */
550/** @} */
551/*---------------------------------------------------------------------------*/
552
553/**
554 * \brief Initialise the uDMA driver
555 *
556 * Prepares the channel control structure and enables the controller
557 */
558void udma_init(void);
559
560/**
561 * \brief Sets the channels source address
562 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
563 * \param src_end The source's end address
564 */
565void udma_set_channel_src(uint8_t channel, uint32_t src_end);
566
567/**
568 * \brief Sets the channel's destination address
569 * \param dst_end The destination's end address
570 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
571 */
572void udma_set_channel_dst(uint8_t channel, uint32_t dst_end);
573
574/**
575 * \brief Configure the channel's control word
576 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
577 * \param ctrl The value of the control word
578 *
579 * The value of the control word is generated by ORing the values defined as
580 * UDMA_CHCTL_xyz
581 *
582 * For example, to configure a channel with 8 bit source and destination size,
583 * 0 source increment and 8 bit destination increment, one would need to pass
584 * UDMA_CHCTL_DSTINC_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_SRCSIZE_8 |
585 * UDMA_CHCTL_DSTSIZE_8
586 *
587 * Macros defined as 0 can be omitted.
588 */
589void udma_set_channel_control_word(uint8_t channel, uint32_t ctrl);
590
591/**
592 * \brief Choose an encoding for a uDMA channel
593 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
594 * \param enc A value in [0 , 4]
595 *
596 * Possible values for the \e encoding param are defined as UDMA_CHnn_xyz
597 */
598void udma_set_channel_assignment(uint8_t channel, uint8_t enc);
599
600/**
601 * \brief Enables a uDMA channel
602 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
603 */
604void udma_channel_enable(uint8_t channel);
605
606/**
607 * \brief Disables a uDMA channel
608 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
609 */
610void udma_channel_disable(uint8_t channel);
611
612/**
613 * \brief Use the alternate control data structure for a channel
614 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
615 *
616 * \note Currently, the driver only reserves memory space for primary contrl
617 * data structures
618 */
619void udma_channel_use_alternate(uint8_t channel);
620
621/**
622 * \brief Use the primary control data structure for a channel
623 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
624 */
625void udma_channel_use_primary(uint8_t channel);
626
627/**
628 * \brief Set a uDMA channel to high priority
629 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
630 */
631void udma_channel_prio_set_high(uint8_t channel);
632
633/**
634 * \brief Set a uDMA channel to default priority
635 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
636 */
637void udma_channel_prio_set_default(uint8_t channel);
638
639/**
640 * \brief Configure a channel to only use burst transfers
641 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
642 *
643 * \note The uDMA controller may under certain conditions automatically disable
644 * burst mode, in which case this function will need to be called again to
645 * re-enable them
646 */
647void udma_channel_use_burst(uint8_t channel);
648
649/**
650 * \brief Configure a channel to use single as well as burst requests
651 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
652 */
653void udma_channel_use_single(uint8_t channel);
654
655/**
656 * \brief Disable peripheral triggers for a uDMA channel
657 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
658 *
659 * Calling this function will result in the uDMA controller not acknowledging
660 * peripheral-generated transfer triggers. Afterwards, the channel may be used
661 * with software triggers
662 */
663void udma_channel_mask_set(uint8_t channel);
664
665/**
666 * \brief Enable peripheral triggers for a uDMA channel
667 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
668 */
669void udma_channel_mask_clr(uint8_t channel);
670
671/**
672 * \brief Generate a software trigger to start a transfer
673 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
674 */
675void udma_channel_sw_request(uint8_t channel);
676
677/**
678 * \brief Retrieve the current mode for a channel
679 * \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
680 * \return The channel's current mode
681 *
682 * The return value will be one of the UDMA_CHCTL_XFERMODE_xyz defines. This
683 * function is useful to determine whether a uDMA transfer has completed, in
684 * which case the return value will be UDMA_CHCTL_XFERMODE_STOP
685 */
686uint8_t udma_channel_get_mode(uint8_t channel);
687
688/**
689 * \brief Calculate the value of the xfersize field in the control structure
690 * \param len The number of items to be transferred
691 * \return The value to be written to the control structure to achieve the
692 * desired transfer size
693 *
694 * If we want to transfer \e len items, we will normally do something like
695 * udma_set_channel_control_word(OTHER_FLAGS | udma_xfer_size(len))
696 */
697#define udma_xfer_size(len) ((len - 1) << 4)
698
699#endif /* UDMA_H_ */
700
701/**
702 * @}
703 * @}
704 */
void udma_set_channel_dst(uint8_t channel, uint32_t dst_end)
Sets the channel's destination address.
Definition: udma.c:80
void udma_init()
Initialise the uDMA driver.
Definition: udma.c:57
void udma_channel_mask_set(uint8_t channel)
Disable peripheral triggers for a uDMA channel.
Definition: udma.c:204
void udma_channel_enable(uint8_t channel)
Enables a uDMA channel.
Definition: udma.c:120
uint8_t udma_channel_get_mode(uint8_t channel)
Retrieve the current mode for a channel.
Definition: udma.c:235
void udma_channel_sw_request(uint8_t channel)
Generate a software trigger to start a transfer.
Definition: udma.c:225
void udma_channel_use_burst(uint8_t channel)
Configure a channel to only use burst transfers.
Definition: udma.c:183
void udma_channel_disable(uint8_t channel)
Disables a uDMA channel.
Definition: udma.c:130
void udma_channel_prio_set_high(uint8_t channel)
Set a uDMA channel to high priority.
Definition: udma.c:162
void udma_channel_mask_clr(uint8_t channel)
Enable peripheral triggers for a uDMA channel.
Definition: udma.c:214
void udma_set_channel_control_word(uint8_t channel, uint32_t ctrl)
Configure the channel's control word.
Definition: udma.c:90
void udma_set_channel_assignment(uint8_t channel, uint8_t enc)
Choose an encoding for a uDMA channel.
Definition: udma.c:100
void udma_channel_use_single(uint8_t channel)
Configure a channel to use single as well as burst requests.
Definition: udma.c:193
void udma_channel_use_primary(uint8_t channel)
Use the primary control data structure for a channel.
Definition: udma.c:151
void udma_channel_prio_set_default(uint8_t channel)
Set a uDMA channel to default priority.
Definition: udma.c:172
void udma_set_channel_src(uint8_t channel, uint32_t src_end)
Sets the channels source address.
Definition: udma.c:70
void udma_channel_use_alternate(uint8_t channel)
Use the alternate control data structure for a channel.
Definition: udma.c:141