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#define | SOC_ADC_ADCCON1 0x400D7000 |
| ADC Control 1.
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#define | SOC_ADC_ADCCON2 0x400D7004 |
| ADC Control 2.
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#define | SOC_ADC_ADCCON3 0x400D7008 |
| ADC Control 3.
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#define | SOC_ADC_ADCL 0x400D700C |
| ADC Result, least significant part.
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#define | SOC_ADC_ADCH 0x400D7010 |
| ADC Result, most significant part.
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#define | SOC_ADC_RNDL 0x400D7014 |
| RNG low byte.
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#define | SOC_ADC_RNDH 0x400D7018 |
| RNG high byte.
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#define | SOC_ADC_CMPCTL 0x400D7024 |
| Analog comparator control and status.
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#define | SOC_ADC_ADCCON1_EOC 0x00000080 |
| End of conversion.
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#define | SOC_ADC_ADCCON1_ST 0x00000040 |
| Start conversion.
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#define | SOC_ADC_ADCCON1_STSEL 0x00000030 |
| Start select.
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#define | SOC_ADC_ADCCON1_RCTRL 0x0000000C |
| Controls the 16-bit RNG.
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#define | SOC_ADC_ADCCON1_RCTRL1 0x00000008 |
| RCTRL high bit.
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#define | SOC_ADC_ADCCON1_RCTRL0 0x00000004 |
| RCTRL low bit.
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#define | SOC_ADC_ADCCON2_SREF 0x000000C0 |
| Reference voltage for sequence.
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#define | SOC_ADC_ADCCON2_SDIV 0x00000030 |
| Decimation rate for sequence.
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#define | SOC_ADC_ADCCON2_SCH 0x0000000F |
| Sequence channel select.
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#define | SOC_ADC_ADCCON3_EREF 0x000000C0 |
| Reference voltage for extra.
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#define | SOC_ADC_ADCCON3_EDIV 0x00000030 |
| Decimation rate for extra.
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#define | SOC_ADC_ADCCON3_ECH 0x0000000F |
| Single channel select.
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#define | SOC_ADC_ADCCON_REF_INT (0 << 6) |
| Internal reference.
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#define | SOC_ADC_ADCCON_REF_EXT_SINGLE (1 << 6) |
| External reference on AIN7 pin.
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#define | SOC_ADC_ADCCON_REF_AVDD5 (2 << 6) |
| AVDD5 pin.
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#define | SOC_ADC_ADCCON_REF_EXT_DIFF (3 << 6) |
| External reference on AIN6-AIN7 differential input.
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#define | SOC_ADC_ADCCON_DIV_64 (0 << 4) |
| 64 decimation rate (7 bits ENOB)
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#define | SOC_ADC_ADCCON_DIV_128 (1 << 4) |
| 128 decimation rate (9 bits ENOB)
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#define | SOC_ADC_ADCCON_DIV_256 (2 << 4) |
| 256 decimation rate (10 bits ENOB)
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#define | SOC_ADC_ADCCON_DIV_512 (3 << 4) |
| 512 decimation rate (12 bits ENOB)
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#define | SOC_ADC_ADCCON_CH_AIN0 0x0 |
| AIN0.
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#define | SOC_ADC_ADCCON_CH_AIN1 0x1 |
| AIN1.
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#define | SOC_ADC_ADCCON_CH_AIN2 0x2 |
| AIN2.
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#define | SOC_ADC_ADCCON_CH_AIN3 0x3 |
| AIN3.
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#define | SOC_ADC_ADCCON_CH_AIN4 0x4 |
| AIN4.
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#define | SOC_ADC_ADCCON_CH_AIN5 0x5 |
| AIN5.
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#define | SOC_ADC_ADCCON_CH_AIN6 0x6 |
| AIN6.
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#define | SOC_ADC_ADCCON_CH_AIN7 0x7 |
| AIN7.
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#define | SOC_ADC_ADCCON_CH_AIN0_AIN1 0x8 |
| AIN0-AIN1.
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#define | SOC_ADC_ADCCON_CH_AIN2_AIN3 0x9 |
| AIN2-AIN3.
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#define | SOC_ADC_ADCCON_CH_AIN4_AIN5 0xA |
| AIN4-AIN5.
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#define | SOC_ADC_ADCCON_CH_AIN6_AIN7 0xB |
| AIN6-AIN7.
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#define | SOC_ADC_ADCCON_CH_GND 0xC |
| GND.
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#define | SOC_ADC_ADCCON_CH_TEMP 0xE |
| Temperature sensor.
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#define | SOC_ADC_ADCCON_CH_VDD_3 0xF |
| VDD/3.
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#define | SOC_ADC_ADCL_ADC 0x000000FC |
| ADC Result, least significant part.
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#define | SOC_ADC_ADCH_ADC 0x000000FF |
| ADC Result, most significant part.
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#define | SOC_ADC_RNDL_RNDL 0x000000FF |
| Random value/seed or CRC result low byte.
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#define | SOC_ADC_RNDH_RNDH 0x000000FF |
| Random value or CRC result/input data, high byte.
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#define | SOC_ADC_CMPCTL_EN 0x00000002 |
| Comparator enable.
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#define | SOC_ADC_CMPCTL_OUTPUT 0x00000001 |
| Comparator output.
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Header file with register declarations for the cc2538 ADC and H/W RNG.
Definition in file soc-adc.h.