Contiki-NG
sky-def.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2010, Swedish Institute of Computer Science.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the Institute nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31/**
32 * \file
33 * A brief description of what this file is
34 * \author
35 * Niclas Finne <nfi@sics.se>
36 * Joakim Eriksson <joakime@sics.se>
37 */
38
39#ifndef SKY_DEF_H_
40#define SKY_DEF_H_
41
42/*
43 * Definitions below are dictated by the hardware and not really
44 * changeable!
45 */
46
47 /* 1 len byte, 2 bytes CRC */
48 #define RADIO_PHY_OVERHEAD 3
49 /* 250kbps data rate. One byte = 32us */
50 #define RADIO_BYTE_AIR_TIME 32
51/* Delay between GO signal and SFD: radio fixed delay + 4Bytes preample + 1B SFD -- 1Byte time is 32us
52 * ~327us + 129preample = 456 us */
53#define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456))
54/* Delay between GO signal and start listening
55 * ~50us delay + 129preample + ?? = 183 us */
56#define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183))
57/* Delay between the SFD finishes arriving and it is detected in software */
58#define RADIO_DELAY_BEFORE_DETECT 0
59
60/* Disable TSCH frame filtering */
61#define TSCH_CONF_HW_FRAME_FILTERING 0
62
63#define PLATFORM_HAS_LEDS 1
64#define PLATFORM_HAS_BUTTON 1
65#define PLATFORM_HAS_LIGHT 1
66#define PLATFORM_HAS_BATTERY 1
67#define PLATFORM_HAS_SHT11 1
68#define PLATFORM_HAS_RADIO 1
69
70/* CPU target speed in Hz */
71#define F_CPU 3900000uL /*2457600uL*/
72
73/* the low-level radio driver */
74#define NETSTACK_CONF_RADIO cc2420_driver
75
76/* LED ports */
77#define LEDS_PxDIR P5DIR
78#define LEDS_PxOUT P5OUT
79#define LEDS_CONF_RED 0x10
80#define LEDS_CONF_GREEN 0x20
81#define LEDS_CONF_YELLOW 0x40
82#define LEDS_CONF_ALL ((LEDS_CONF_RED) | (LEDS_CONF_GREEN) | (LEDS_CONF_YELLOW))
83
84#define LEDS_CONF_LEGACY_API 1
85
86/* DCO speed resynchronization for more robust UART, etc. */
87#ifndef DCOSYNCH_CONF_ENABLED
88#define DCOSYNCH_CONF_ENABLED (!(MAC_CONF_WITH_TSCH)) /* TSCH needs timerB
89for SFD timestamping */
90#endif /* DCOSYNCH_CONF_ENABLED */
91
92#ifndef CC2420_CONF_SFD_TIMESTAMPS
93#define CC2420_CONF_SFD_TIMESTAMPS (MAC_CONF_WITH_TSCH) /* TSCH needs SFD timestamping */
94#endif /* CC2420_CONF_SFD_TIMESTAMPS */
95
96#ifndef DCOSYNCH_CONF_PERIOD
97#define DCOSYNCH_CONF_PERIOD 30
98#endif /* DCOSYNCH_CONF_PERIOD */
99
100#define ROM_ERASE_UNIT_SIZE 512
101#define XMEM_ERASE_UNIT_SIZE (64*1024L)
102
103
104#define CFS_CONF_OFFSET_TYPE long
105
106
107/* Use the first 64k of external flash for node configuration */
108#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
109
110/* Use the second 64k of external flash for codeprop. */
111#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
112
113#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
114#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
115
116#define CFS_RAM_CONF_SIZE 4096
117
118/*
119 * SPI bus configuration for the TMote Sky.
120 */
121
122/* SPI input/output registers. */
123#define SPI_TXBUF U0TXBUF
124#define SPI_RXBUF U0RXBUF
125
126 /* USART0 Tx ready? */
127#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
128 /* USART0 Rx ready? */
129#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
130 /* USART0 Tx buffer ready? */
131#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
132
133#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
134#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
135#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
136
137/*
138 * SPI bus - M25P80 external flash configuration.
139 */
140
141#define FLASH_PWR 3 /* P4.3 Output */
142#define FLASH_CS 4 /* P4.4 Output */
143#define FLASH_HOLD 7 /* P4.7 Output */
144
145/* Enable/disable flash access to the SPI bus (active low). */
146
147#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
148#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
149
150#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
151#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
152
153/*
154 * SPI bus - CC2420 pin configuration.
155 */
156
157#define CC2420_CONF_SYMBOL_LOOP_COUNT 800
158
159/* P1.0 - Input: FIFOP from CC2420 */
160#define CC2420_FIFOP_PORT(type) P1##type
161#define CC2420_FIFOP_PIN 0
162/* P1.3 - Input: FIFO from CC2420 */
163#define CC2420_FIFO_PORT(type) P1##type
164#define CC2420_FIFO_PIN 3
165/* P1.4 - Input: CCA from CC2420 */
166#define CC2420_CCA_PORT(type) P1##type
167#define CC2420_CCA_PIN 4
168/* P4.1 - Input: SFD from CC2420 */
169#define CC2420_SFD_PORT(type) P4##type
170#define CC2420_SFD_PIN 1
171/* P4.2 - Output: SPI Chip Select (CS_N) */
172#define CC2420_CSN_PORT(type) P4##type
173#define CC2420_CSN_PIN 2
174/* P4.5 - Output: VREG_EN to CC2420 */
175#define CC2420_VREG_PORT(type) P4##type
176#define CC2420_VREG_PIN 5
177/* P4.6 - Output: RESET_N to CC2420 */
178#define CC2420_RESET_PORT(type) P4##type
179#define CC2420_RESET_PIN 6
180
181#define CC2420_IRQ_VECTOR PORT1_VECTOR
182
183/* Pin status. */
184#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
185#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
186#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
187#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
188
189/* The CC2420 reset pin. */
190#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
191#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
192
193/* CC2420 voltage regulator enable pin. */
194#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
195#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
196
197/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
198#define CC2420_FIFOP_INT_INIT() do { \
199 CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
200 CC2420_CLEAR_FIFOP_INT(); \
201 } while(0)
202
203/* FIFOP on external interrupt 0. */
204#define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
205#define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
206#define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
207
208/*
209 * Enables/disables CC2420 access to the SPI bus (not the bus).
210 * (Chip Select)
211 */
212
213 /* ENABLE CSn (active low) */
214#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
215 /* DISABLE CSn (active low) */
216#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
217#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
218
219/* Platform-specific define for the end of the stack region */
220#define STACK_CONF_ORIGIN ((void *)0x3900)
221
222#endif /* SKY_DEF_H_ */