|
|
#define | CENTHS_ADDR 0x00 |
|
#define | SEC_ADDR 0x01 |
|
#define | MIN_ADDR 0x02 |
|
#define | HOUR_ADDR 0x03 |
|
#define | DAY_ADDR 0x04 |
|
#define | MONTHS_ADDR 0x05 |
|
#define | YEAR_ADDR 0x06 |
|
#define | WEEKDAYLS_ADDR 0x07 |
|
#define | ALARM_MAP_OFFSET 0x08 |
|
#define | HUNDREDTHS_ALARM_ADDR 0x00 |
|
#define | SECONDS_ALARM_ADDR 0x01 |
|
#define | MINUTES_ALARM_ADDR 0x02 |
|
#define | HOURS_ALARM_ADDR 0x03 |
|
#define | DAY_ALARMS_ADDR 0x04 |
|
#define | MONTHS_ALARM_ADDR 0x05 |
|
#define | WEEKDAYS_ALARM_ADDR 0x06 |
|
#define | CONFIG_MAP_OFFSET 0x0F |
|
#define | STATUS_ADDR 0x00 |
|
#define | CTRL_1_ADDR 0x01 |
|
#define | CTRL_2_ADDR 0x02 |
|
#define | INT_MASK_ADDR 0x03 |
|
#define | SQW_ADDR 0x04 |
|
#define | CAL_XT_ADDR 0x05 |
|
#define | CAL_RC_HI_ADDR 0x06 |
|
#define | CAL_RC_LO_ADDR 0x07 |
|
#define | INT_POL_ADDR 0x08 |
|
#define | TIMER_CONTROL_ADDR 0x09 |
|
#define | TIMER_COUNTDOWN_ADDR 0x0A |
|
#define | TIMER_INITIAL_ADDR 0x0B |
|
#define | WDT_ADDR 0x0C |
|
#define | OSC_CONTROL_ADDR 0x0D |
|
#define | OSC_STATUS_ADDR 0x0E |
|
#define | CONF_KEY_ADDR 0x10 |
|
#define | TRICKLE_ADDR 0x11 |
|
#define | BREF_CTRL_ADDR 0x12 |
|
#define | AF_CTRL_ADDR 0x17 |
|
#define | BAT_MODE_IO_ADDR 0x18 |
|
#define | ASTAT_ADDR 0x20 |
|
#define | OCTRL_ADDR 0x21 |
|
#define | EXT_ADDR 0x30 |
|
#define | RAM_1_ADDR (CONFIG_MAP_OFFSET + 0x31) |
|
#define | RAM_2_ADDR (CONFIG_MAP_OFFSET + 0x71) |
|
|
#define | STATUS_CB 0x80 |
|
#define | STATUS_BAT 0x40 |
|
#define | STATUS_WDT 0x20 |
|
#define | STATUS_BL 0x10 |
|
#define | STATUS_TIM 0x08 |
|
#define | STATUS_ALM 0x04 |
|
#define | STATUS_EX2 0x02 |
|
#define | STATUS_EX1 0x01 |
|
#define | CTRL1_WRTC 0x01 |
|
#define | CTRL1_ARST 0x04 |
|
#define | CTRL1_OUT 0x10 |
|
#define | CTRL1_OUTB 0x20 |
|
#define | CTRL1_1224 0x40 |
|
#define | CTRL1_STOP 0x80 |
|
#define | CTRL2_OUT1S_NIRQ_OUT 0x00 |
|
#define | CTRL2_OUT1S_NIRQ_SQW_OUT 0x01 |
|
#define | CTRL2_OUT1S_NIRQ_SQW_NIRQ 0x02 |
|
#define | CTRL2_OUT1S_NIRQ_NAIRQ_OUT 0x03 |
|
#define | CTRL2_OUT2S_SQW_OUT 0x04 |
|
#define | CTRL2_OUT2S_NAIRQ_OUTB 0x0C |
|
#define | CTRL2_OUT2S_TIRQ_OUTB 0x10 |
|
#define | CTRL2_OUT2S_NTIRQ_OUTB 0x14 |
|
#define | CTRL2_OUT2S_OUTB 0x1C |
|
#define | INTMASK_EX1E 0x01 |
|
#define | INTMASK_EX2E 0x02 |
|
#define | INTMASK_AIE 0x04 |
|
#define | INTMASK_TIE 0x08 |
|
#define | INTMASK_BLIE 0x10 |
|
#define | INTMASK_IM_HIGH 0x20 |
|
#define | INTMASK_IM_MED 0x40 |
|
#define | INTMASK_IM_LOW 0x60 |
|
#define | INTMASK_CEB 0x80 |
|
#define | COUNTDOWN_TIMER_TE 0x80 |
|
#define | COUNTDOWN_TIMER_TM 0x40 |
|
#define | COUNTDOWN_TIMER_TRPT 0x20 |
|
#define | COUNTDOWN_TIMER_RPT_SECOND 0x1C |
|
#define | COUNTDOWN_TIMER_RPT_MINUTE 0x18 |
|
#define | COUNTDOWN_TIMER_RPT_HOUR 0x24 |
|
#define | COUNTDOWN_TIMER_RPT_DAY 0x10 |
|
#define | COUNTDOWN_TIMER_RPT_WEEK 0x0C |
|
#define | COUNTDOWN_TIMER_RPT_MONTH 0x08 |
|
#define | COUNTDOWN_TIMER_RPT_YEAR 0x04 |
|
#define | COUNTDOWN_TIMER_RPT_SHIFT 0x02 |
|
#define | COUNTDOWN_TIMER_TFS_ONE 0x01 |
|
#define | COUNTDOWN_TIMER_TFS_TWO 0x02 |
|
#define | COUNTDOWN_TIMER_TFS_THREE 0x03 |
|
#define | OSCONTROL_ACIE 0x01 |
|
#define | OSCONTROL_OFIE 0x02 |
|
#define | OSCONTROL_FOS 0x08 |
|
#define | OSCONTROL_AOS 0x10 |
|
#define | OSCONTROL_ACAL_NO_CAL 0x00 |
|
#define | OSCONTROL_ACAL_17_MIN 0x40 |
|
#define | OSCONTROL_ACAL_9_MIN 0x60 |
|
#define | OSCONTROL_OSEL 0x80 |
|
|
#define | AB08XX_ADDR 0x69 |
|
#define | INT_BUFF_SIZE 20L |
|
#define | TCS_DIODE_3K (TCS_ENABLE + 0x05) |
|
#define | TCS_DIODE_6K (TCS_ENABLE + 0x06) |
|
#define | TCS_DIODE_11K (TCS_ENABLE + 0x07) |
|
#define | RTCC_TOGGLE_PM_BIT 0x20 |
|
#define | RTCC_FIX_10THS_HUNDRETHS 0xF0 |
|
#define | RTCC_FIX_100THS_HUNDRETHS 0xFF |
|
#define | RTCC_TD_MAP_SIZE (WEEKDAYLS_ADDR + 1) |
|
#define | RTCC_ALARM_MAP_SIZE (WEEKDAYS_ALARM_ADDR + 1) |
|
#define | RTCC_CONFIG_MAP_SIZE (BREF_CTRL_ADDR + 1) |
|
|
#define | AB08_ERROR (-1) |
|
#define | AB08_SUCCESS 0x00 |
|
Header file for the RE-Mote RF antenna switch.
Definition in file rtcc.h.