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44#define RFCORE_XREG_FRMFILT0 0x40088600
45#define RFCORE_XREG_FRMFILT1 0x40088604
46#define RFCORE_XREG_SRCMATCH 0x40088608
47#define RFCORE_XREG_SRCSHORTEN0 0x4008860C
48#define RFCORE_XREG_SRCSHORTEN1 0x40088610
49#define RFCORE_XREG_SRCSHORTEN2 0x40088614
50#define RFCORE_XREG_SRCEXTEN0 0x40088618
51#define RFCORE_XREG_SRCEXTEN1 0x4008861C
52#define RFCORE_XREG_SRCEXTEN2 0x40088620
53#define RFCORE_XREG_FRMCTRL0 0x40088624
54#define RFCORE_XREG_FRMCTRL1 0x40088628
55#define RFCORE_XREG_RXENABLE 0x4008862C
56#define RFCORE_XREG_RXMASKSET 0x40088630
57#define RFCORE_XREG_RXMASKCLR 0x40088634
58#define RFCORE_XREG_FREQTUNE 0x40088638
59#define RFCORE_XREG_FREQCTRL 0x4008863C
60#define RFCORE_XREG_TXPOWER 0x40088640
61#define RFCORE_XREG_TXCTRL 0x40088644
62#define RFCORE_XREG_FSMSTAT0 0x40088648
63#define RFCORE_XREG_FSMSTAT1 0x4008864C
64#define RFCORE_XREG_FIFOPCTRL 0x40088650
65#define RFCORE_XREG_FSMCTRL 0x40088654
66#define RFCORE_XREG_CCACTRL0 0x40088658
67#define RFCORE_XREG_CCACTRL1 0x4008865C
68#define RFCORE_XREG_RSSI 0x40088660
69#define RFCORE_XREG_RSSISTAT 0x40088664
70#define RFCORE_XREG_RXFIRST 0x40088668
71#define RFCORE_XREG_RXFIFOCNT 0x4008866C
72#define RFCORE_XREG_TXFIFOCNT 0x40088670
73#define RFCORE_XREG_RXFIRST_PTR 0x40088674
74#define RFCORE_XREG_RXLAST_PTR 0x40088678
75#define RFCORE_XREG_RXP1_PTR 0x4008867C
76#define RFCORE_XREG_RXP2_PTR 0x40088680
77#define RFCORE_XREG_TXFIRST_PTR 0x40088684
78#define RFCORE_XREG_TXLAST_PTR 0x40088688
79#define RFCORE_XREG_RFIRQM0 0x4008868C
80#define RFCORE_XREG_RFIRQM1 0x40088690
81#define RFCORE_XREG_RFERRM 0x40088694
82#define RFCORE_XREG_D18_SPARE_OPAMPMC 0x40088698
83#define RFCORE_XREG_RFRND 0x4008869C
84#define RFCORE_XREG_MDMCTRL0 0x400886A0
85#define RFCORE_XREG_MDMCTRL1 0x400886A4
86#define RFCORE_XREG_FREQEST 0x400886A8
87#define RFCORE_XREG_RXCTRL 0x400886AC
88#define RFCORE_XREG_FSCTRL 0x400886B0
89#define RFCORE_XREG_FSCAL1 0x400886B8
90#define RFCORE_XREG_FSCAL2 0x400886BC
91#define RFCORE_XREG_FSCAL3 0x400886C0
92#define RFCORE_XREG_AGCCTRL0 0x400886C4
93#define RFCORE_XREG_AGCCTRL1 0x400886C8
94#define RFCORE_XREG_AGCCTRL2 0x400886CC
95#define RFCORE_XREG_AGCCTRL3 0x400886D0
96#define RFCORE_XREG_ADCTEST0 0x400886D4
97#define RFCORE_XREG_ADCTEST1 0x400886D8
98#define RFCORE_XREG_ADCTEST2 0x400886DC
99#define RFCORE_XREG_MDMTEST0 0x400886E0
100#define RFCORE_XREG_MDMTEST1 0x400886E4
101#define RFCORE_XREG_DACTEST0 0x400886E8
102#define RFCORE_XREG_DACTEST1 0x400886EC
103#define RFCORE_XREG_DACTEST2 0x400886F0
104#define RFCORE_XREG_ATEST 0x400886F4
105#define RFCORE_XREG_PTEST0 0x400886F8
106#define RFCORE_XREG_PTEST1 0x400886FC
107#define RFCORE_XREG_CSPPROG0 0x40088700
108#define RFCORE_XREG_CSPPROG1 0x40088704
109#define RFCORE_XREG_CSPPROG2 0x40088708
110#define RFCORE_XREG_CSPPROG3 0x4008870C
111#define RFCORE_XREG_CSPPROG4 0x40088710
112#define RFCORE_XREG_CSPPROG5 0x40088714
113#define RFCORE_XREG_CSPPROG6 0x40088718
114#define RFCORE_XREG_CSPPROG7 0x4008871C
115#define RFCORE_XREG_CSPPROG8 0x40088720
116#define RFCORE_XREG_CSPPROG9 0x40088724
117#define RFCORE_XREG_CSPPROG10 0x40088728
118#define RFCORE_XREG_CSPPROG11 0x4008872C
119#define RFCORE_XREG_CSPPROG12 0x40088730
120#define RFCORE_XREG_CSPPROG13 0x40088734
121#define RFCORE_XREG_CSPPROG14 0x40088738
122#define RFCORE_XREG_CSPPROG15 0x4008873C
123#define RFCORE_XREG_CSPPROG16 0x40088740
124#define RFCORE_XREG_CSPPROG17 0x40088744
125#define RFCORE_XREG_CSPPROG18 0x40088748
126#define RFCORE_XREG_CSPPROG19 0x4008874C
127#define RFCORE_XREG_CSPPROG20 0x40088750
128#define RFCORE_XREG_CSPPROG21 0x40088754
129#define RFCORE_XREG_CSPPROG22 0x40088758
130#define RFCORE_XREG_CSPPROG23 0x4008875C
131#define RFCORE_XREG_CSPCTRL 0x40088780
132#define RFCORE_XREG_CSPSTAT 0x40088784
133#define RFCORE_XREG_CSPX 0x40088788
134#define RFCORE_XREG_CSPY 0x4008878C
135#define RFCORE_XREG_CSPZ 0x40088790
136#define RFCORE_XREG_CSPT 0x40088794
137#define RFCORE_XREG_RFC_DUTY_CYCLE 0x400887A0
138#define RFCORE_XREG_RFC_OBS_CTRL0 0x400887AC
139#define RFCORE_XREG_RFC_OBS_CTRL1 0x400887B0
140#define RFCORE_XREG_RFC_OBS_CTRL2 0x400887B4
141#define RFCORE_XREG_TXFILTCFG 0x400887E8
147#define RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION 0x0000000C
148#define RFCORE_XREG_FRMFILT0_PAN_COORDINATOR 0x00000002
149#define RFCORE_XREG_FRMFILT0_FRAME_FILTER_EN 0x00000001
155#define RFCORE_XREG_FRMFILT1_ACCEPT_FT_3_MAC_CMD 0x00000040
156#define RFCORE_XREG_FRMFILT1_ACCEPT_FT_2_ACK 0x00000020
157#define RFCORE_XREG_FRMFILT1_ACCEPT_FT_1_DATA 0x00000010
158#define RFCORE_XREG_FRMFILT1_ACCEPT_FT_0_BEACON 0x00000008
159#define RFCORE_XREG_FRMFILT1_MODIFY_FT_FILTER 0x00000006
165#define RFCORE_XREG_SRCMATCH_PEND_DATAREQ_ONLY 0x00000004
166#define RFCORE_XREG_SRCMATCH_AUTOPEND 0x00000002
167#define RFCORE_XREG_SRCMATCH_SRC_MATCH_EN 0x00000001
173#define RFCORE_XREG_SRCSHORTEN0_SHORT_ADDR_EN 0x000000FF
179#define RFCORE_XREG_SRCSHORTEN1_SHORT_ADDR_EN 0x000000FF
185#define RFCORE_XREG_SRCSHORTEN2_SHORT_ADDR_EN 0x000000FF
191#define RFCORE_XREG_SRCEXTEN0_EXT_ADDR_EN 0x000000FF
197#define RFCORE_XREG_SRCEXTEN1_EXT_ADDR_EN 0x000000FF
203#define RFCORE_XREG_SRCEXTEN2_EXT_ADDR_EN 0x000000FF
209#define RFCORE_XREG_FRMCTRL0_APPEND_DATA_MODE 0x00000080
210#define RFCORE_XREG_FRMCTRL0_AUTOCRC 0x00000040
211#define RFCORE_XREG_FRMCTRL0_AUTOACK 0x00000020
212#define RFCORE_XREG_FRMCTRL0_ENERGY_SCAN 0x00000010
213#define RFCORE_XREG_FRMCTRL0_RX_MODE 0x0000000C
214#define RFCORE_XREG_FRMCTRL0_TX_MODE 0x00000003
220#define RFCORE_XREG_FRMCTRL1_PENDING_OR 0x00000004
221#define RFCORE_XREG_FRMCTRL1_IGNORE_TX_UNDERF 0x00000002
222#define RFCORE_XREG_FRMCTRL1_SET_RXENMASK_ON_TX 0x00000001
228#define RFCORE_XREG_RXENABLE_RXENMASK 0x000000FF
234#define RFCORE_XREG_RXMASKSET_RXENMASKSET 0x000000FF
240#define RFCORE_XREG_RXMASKCLR_RXENMASKCLR 0x000000FF
246#define RFCORE_XREG_FREQTUNE_XOSC32M_TUNE 0x0000000F
252#define RFCORE_XREG_FREQCTRL_FREQ 0x0000007F
258#define RFCORE_XREG_TXPOWER_PA_POWER 0x000000F0
259#define RFCORE_XREG_TXPOWER_PA_BIAS 0x0000000F
265#define RFCORE_XREG_TXCTRL_DAC_CURR 0x00000070
266#define RFCORE_XREG_TXCTRL_DAC_DC 0x0000000C
267#define RFCORE_XREG_TXCTRL_TXMIX_CURRENT 0x00000003
273#define RFCORE_XREG_FSMSTAT0_CAL_DONE 0x00000080
274#define RFCORE_XREG_FSMSTAT0_CAL_RUNNING 0x00000040
275#define RFCORE_XREG_FSMSTAT0_FSM_FFCTRL_STATE 0x0000003F
281#define RFCORE_XREG_FSMSTAT1_FIFO 0x00000080
282#define RFCORE_XREG_FSMSTAT1_FIFOP 0x00000040
283#define RFCORE_XREG_FSMSTAT1_SFD 0x00000020
284#define RFCORE_XREG_FSMSTAT1_CCA 0x00000010
285#define RFCORE_XREG_FSMSTAT1_SAMPLED_CCA 0x00000008
286#define RFCORE_XREG_FSMSTAT1_LOCK_STATUS 0x00000004
287#define RFCORE_XREG_FSMSTAT1_TX_ACTIVE 0x00000002
288#define RFCORE_XREG_FSMSTAT1_RX_ACTIVE 0x00000001
294#define RFCORE_XREG_FIFOPCTRL_FIFOP_THR 0x0000007F
300#define RFCORE_XREG_FSMCTRL_SLOTTED_ACK 0x00000002
301#define RFCORE_XREG_FSMCTRL_RX2RX_TIME_OFF 0x00000001
307#define RFCORE_XREG_CCACTRL0_CCA_THR 0x000000FF
313#define RFCORE_XREG_CCACTRL1_CCA_MODE 0x00000018
314#define RFCORE_XREG_CCACTRL1_CCA_HYST 0x00000007
320#define RFCORE_XREG_RSSI_RSSI_VAL 0x000000FF
321#define RFCORE_XREG_RSSI_RSSI_VAL_S 0
327#define RFCORE_XREG_RSSISTAT_RSSI_VALID 0x00000001
333#define RFCORE_XREG_RXFIRST_DATA 0x000000FF
339#define RFCORE_XREG_RXFIFOCNT_RXFIFOCNT 0x000000FF
345#define RFCORE_XREG_TXFIFOCNT_TXFIFOCNT 0x000000FF
351#define RFCORE_XREG_RXFIRST_PTR_RXFIRST_PTR 0x000000FF
352#define RFCORE_XREG_RXLAST_PTR_RXLAST_PTR 0x000000FF
353#define RFCORE_XREG_RXP1_PTR_RXP1_PTR 0x000000FF
354#define RFCORE_XREG_RXP2_PTR_RXP2_PTR 0x000000FF
360#define RFCORE_XREG_TXFIRST_PTR_TXFIRST_PTR 0x000000FF
361#define RFCORE_XREG_TXLAST_PTR_TXLAST_PTR 0x000000FF
367#define RFCORE_XREG_RFIRQM0_RFIRQM 0x000000FF
368#define RFCORE_XREG_RFIRQM0_RXMASKZERO 0x00000080
369#define RFCORE_XREG_RFIRQM0_RXPKTDONE 0x00000040
370#define RFCORE_XREG_RFIRQM0_FRAME_ACCEPTED 0x00000020
371#define RFCORE_XREG_RFIRQM0_SRC_MATCH_FOUND 0x00000010
372#define RFCORE_XREG_RFIRQM0_SRC_MATCH_DONE 0x00000008
373#define RFCORE_XREG_RFIRQM0_FIFOP 0x00000004
374#define RFCORE_XREG_RFIRQM0_SFD 0x00000002
375#define RFCORE_XREG_RFIRQM0_ACT_UNUSED 0x00000001
381#define RFCORE_XREG_RFIRQM1_RFIRQM 0x0000003F
382#define RFCORE_XREG_RFIRQM1_CSP_WAIT 0x00000020
383#define RFCORE_XREG_RFIRQM1_CSP_STOP 0x00000010
384#define RFCORE_XREG_RFIRQM1_CSP_MANINT 0x00000008
385#define RFCORE_XREG_RFIRQM1_RFIDLE 0x00000004
386#define RFCORE_XREG_RFIRQM1_TXDONE 0x00000002
387#define RFCORE_XREG_RFIRQM1_TXACKDONE 0x00000001
393#define RFCORE_XREG_RFERRM_RFERRM 0x0000007F
394#define RFCORE_XREG_RFERRM_STROBEERR 0x00000040
395#define RFCORE_XREG_RFERRM_TXUNDERF 0x00000020
396#define RFCORE_XREG_RFERRM_TXOVERF 0x00000010
397#define RFCORE_XREG_RFERRM_RXUNDERF 0x00000008
398#define RFCORE_XREG_RFERRM_RXOVERF 0x00000004
399#define RFCORE_XREG_RFERRM_RXABO 0x00000002
400#define RFCORE_XREG_RFERRM_NLOCK 0x00000001
406#define RFCORE_XREG_D18_SPARE_OPAMPMC_MODE 0x00000003
412#define RFCORE_XREG_RFRND_QRND 0x00000002
413#define RFCORE_XREG_RFRND_IRND 0x00000001
419#define RFCORE_XREG_MDMCTRL0_DEM_NUM_ZEROS 0x000000C0
420#define RFCORE_XREG_MDMCTRL0_DEMOD_AVG_MODE 0x00000020
421#define RFCORE_XREG_MDMCTRL0_PREAMBLE_LENGTH 0x0000001E
422#define RFCORE_XREG_MDMCTRL0_TX_FILTER 0x00000001
428#define RFCORE_XREG_MDMCTRL1_CORR_THR_SFD 0x00000020
429#define RFCORE_XREG_MDMCTRL1_CORR_THR 0x0000001F
435#define RFCORE_XREG_FREQEST_FREQEST 0x000000FF
441#define RFCORE_XREG_RXCTRL_GBIAS_LNA2_REF 0x00000030
442#define RFCORE_XREG_RXCTRL_GBIAS_LNA_REF 0x0000000C
443#define RFCORE_XREG_RXCTRL_MIX_CURRENT 0x00000003
449#define RFCORE_XREG_FSCTRL_PRE_CURRENT 0x000000C0
450#define RFCORE_XREG_FSCTRL_LODIV_BUF_CURRENT_TX 0x00000030
451#define RFCORE_XREG_FSCTRL_LODIV_BUF_CURRENT_RX 0x0000000C
452#define RFCORE_XREG_FSCTRL_LODIV_CURRENT 0x00000003
458#define RFCORE_XREG_FSCAL1_VCO_CURR_CAL_OE 0x00000080
459#define RFCORE_XREG_FSCAL1_VCO_CURR_CAL 0x0000007C
460#define RFCORE_XREG_FSCAL1_VCO_CURR 0x00000003
466#define RFCORE_XREG_FSCAL2_VCO_CAPARR_OE 0x00000040
467#define RFCORE_XREG_FSCAL2_VCO_CAPARR 0x0000003F
473#define RFCORE_XREG_FSCAL3_VCO_DAC_EN_OV 0x00000040
474#define RFCORE_XREG_FSCAL3_VCO_VC_DAC 0x0000003C
475#define RFCORE_XREG_FSCAL3_VCO_CAPARR_CAL_CTRL 0x00000003
481#define RFCORE_XREG_AGCCTRL0_AGC_DR_XTND_EN 0x00000040
482#define RFCORE_XREG_AGCCTRL0_AGC_DR_XTND_THR 0x0000003F
488#define RFCORE_XREG_AGCCTRL1_AGC_REF 0x0000003F
494#define RFCORE_XREG_AGCCTRL2_LNA1_CURRENT 0x000000C0
495#define RFCORE_XREG_AGCCTRL2_LNA2_CURRENT 0x00000038
496#define RFCORE_XREG_AGCCTRL2_LNA3_CURRENT 0x00000006
497#define RFCORE_XREG_AGCCTRL2_LNA_CURRENT_OE 0x00000001
503#define RFCORE_XREG_AGCCTRL3_AGC_SETTLE_WAIT 0x00000060
504#define RFCORE_XREG_AGCCTRL3_AGC_WIN_SIZE 0x00000018
505#define RFCORE_XREG_AGCCTRL3_AAF_RP 0x00000006
506#define RFCORE_XREG_AGCCTRL3_AAF_RP_OE 0x00000001
512#define RFCORE_XREG_ADCTEST0_ADC_VREF_ADJ 0x000000C0
513#define RFCORE_XREG_ADCTEST0_ADC_QUANT_ADJ 0x00000030
514#define RFCORE_XREG_ADCTEST0_ADC_GM_ADJ 0x0000000E
515#define RFCORE_XREG_ADCTEST0_ADC_DAC2_EN 0x00000001
521#define RFCORE_XREG_ADCTEST1_ADC_TEST_CTRL 0x000000F0
522#define RFCORE_XREG_ADCTEST1_ADC_C2_ADJ 0x0000000C
523#define RFCORE_XREG_ADCTEST1_ADC_C3_ADJ 0x00000003
529#define RFCORE_XREG_ADCTEST2_ADC_TEST_MODE 0x00000060
530#define RFCORE_XREG_ADCTEST2_AAF_RS 0x00000018
531#define RFCORE_XREG_ADCTEST2_ADC_FF_ADJ 0x00000006
532#define RFCORE_XREG_ADCTEST2_ADC_DAC_ROT 0x00000001
538#define RFCORE_XREG_MDMTEST0_TX_TONE 0x000000F0
539#define RFCORE_XREG_MDMTEST0_DC_WIN_SIZE 0x0000000C
540#define RFCORE_XREG_MDMTEST0_DC_BLOCK_MODE 0x00000003
546#define RFCORE_XREG_MDMTEST1_USEMIRROR_IF 0x00000020
547#define RFCORE_XREG_MDMTEST1_MOD_IF 0x00000010
548#define RFCORE_XREG_MDMTEST1_RAMP_AMP 0x00000008
549#define RFCORE_XREG_MDMTEST1_RFC_SNIFF_EN 0x00000004
550#define RFCORE_XREG_MDMTEST1_MODULATION_MODE 0x00000002
551#define RFCORE_XREG_MDMTEST1_LOOPBACK_EN 0x00000001
557#define RFCORE_XREG_DACTEST0_DAC_Q 0x400886FF
563#define RFCORE_XREG_DACTEST1_DAC_I 0x400886FF
569#define RFCORE_XREG_DACTEST2_DAC_DEM_EN 0x00000020
570#define RFCORE_XREG_DACTEST2_DAC_CASC_CTRL 0x00000018
571#define RFCORE_XREG_DACTEST2_DAC_SRC 0x00000007
577#define RFCORE_XREG_ATEST_ATEST_CTRL 0x0000003F
578#define RFCORE_XREG_ATEST_ATEST_CTRL_DIS 0x00000000
579#define RFCORE_XREG_ATEST_ATEST_CTRL_TEMP 0x00000001
585#define RFCORE_XREG_PTEST0_PRE_PD 0x00000080
586#define RFCORE_XREG_PTEST0_CHP_PD 0x00000040
587#define RFCORE_XREG_PTEST0_ADC_PD 0x00000020
588#define RFCORE_XREG_PTEST0_DAC_PD 0x00000010
589#define RFCORE_XREG_PTEST0_LNA_PD 0x0000000C
590#define RFCORE_XREG_PTEST0_TXMIX_PD 0x00000002
591#define RFCORE_XREG_PTEST0_AAF_PD 0x00000001
597#define RFCORE_XREG_PTEST1_PD_OVERRIDE 0x00000008
598#define RFCORE_XREG_PTEST1_PA_PD 0x00000004
599#define RFCORE_XREG_PTEST1_VCO_PD 0x00000002
600#define RFCORE_XREG_PTEST1_LODIV_PD 0x00000001
606#define RFCORE_XREG_CSPPROG_CSP_INSTR 0x000000FF
612#define RFCORE_XREG_CSPCTRL_MCU_CTRL 0x00000001
618#define RFCORE_XREG_CSPSTAT_CSP_RUNNING 0x00000020
619#define RFCORE_XREG_CSPSTAT_CSP_PC 0x0000001F
625#define RFCORE_XREG_CSPX_CSPX 0x000000FF
631#define RFCORE_XREG_CSPY_CSPY 0x000000FF
637#define RFCORE_XREG_CSPZ_CSPZ 0x000000FF
643#define RFCORE_XREG_CSPT_CSPT 0x000000FF
649#define RFCORE_XREG_RFC_DUTY_CYCLE_SWD_EN 0x00000040
650#define RFCORE_XREG_RFC_DUTY_CYCLE_DTC_DCCAL_MODE 0x00000030
651#define RFCORE_XREG_RFC_DUTY_CYCLE_DUTYCYCLE_CNF 0x0000000E
652#define RFCORE_XREG_RFC_DUTY_CYCLE_DUTYCYCLE_EN 0x00000001
658#define RFCORE_XREG_RFC_OBS_CTRL0_RFC_OBS_POL0 0x00000040
659#define RFCORE_XREG_RFC_OBS_CTRL0_RFC_OBS_MUX0 0x0000003F
660#define RFCORE_XREG_RFC_OBS_CTRL1_RFC_OBS_POL1 0x00000040
661#define RFCORE_XREG_RFC_OBS_CTRL1_RFC_OBS_MUX1 0x0000003F
662#define RFCORE_XREG_RFC_OBS_CTRL2_RFC_OBS_POL2 0x00000040
663#define RFCORE_XREG_RFC_OBS_CTRL2_RFC_OBS_MUX2 0x0000003F
669#define RFCORE_XREG_TXFILTCFG_FC 0x0000000F