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#define | USB_ADDR 0x40089000 |
| Function address.
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#define | USB_POW 0x40089004 |
| Power/Control register.
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#define | USB_IIF 0x40089008 |
| IN EPs and EP0 interrupt flags.
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#define | USB_OIF 0x40089010 |
| OUT endpoint interrupt flags.
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#define | USB_CIF 0x40089018 |
| Common USB interrupt flags.
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#define | USB_IIE 0x4008901C |
| IN EPs and EP0 interrupt mask.
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#define | USB_OIE 0x40089024 |
| Out EPs interrupt-enable mask.
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#define | USB_CIE 0x4008902C |
| Common USB interrupt mask.
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#define | USB_FRML 0x40089030 |
| Current frame number (low byte)
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#define | USB_FRMH 0x40089034 |
| Current frame number (high)
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#define | USB_INDEX 0x40089038 |
| Current endpoint index register.
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#define | USB_CTRL 0x4008903C |
| USB control register.
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#define | USB_MAXI 0x40089040 |
| MAX packet size for IN EPs{1-5}.
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#define | USB_CS0_CSIL 0x40089044 |
| EP0 Control and Status or IN EPs control and status (low)
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#define | USB_CS0 0x40089044 |
| EP0 Control and Status (Alias for USB_CS0_CSIL)
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#define | USB_CSIL 0x40089044 |
| IN EPs control and status (low) (Alias for USB_CS0_CSIL)
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#define | USB_CSIH 0x40089048 |
| IN EPs control and status (high)
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#define | USB_MAXO 0x4008904C |
| MAX packet size for OUT EPs.
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#define | USB_CSOL 0x40089050 |
| OUT EPs control and status (low)
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#define | USB_CSOH 0x40089054 |
| OUT EPs control and status (high)
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#define | USB_CNT0_CNTL 0x40089058 |
| Number of RX bytes in EP0 FIFO or number of bytes in EP{1-5} OUT FIFO (low)
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#define | USB_CNT0 0x40089058 |
| Number of RX bytes in EP0 FIFO (Alias for USB_CNT0_CNTL)
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#define | USB_CNTL 0x40089058 |
| Number of bytes in EP{1-5} OUT FIFO (low) (Alias for USB_CNT0_CNTL)
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#define | USB_CNTH 0x4008905C |
| Number of bytes in EP{1-5} OUT FIFO (high)
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#define | USB_F0 0x40089080 |
| Endpoint-0 FIFO.
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#define | USB_F1 0x40089088 |
| Endpoint-1 FIFO.
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#define | USB_F2 0x40089090 |
| Endpoint-2 FIFO.
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#define | USB_F3 0x40089098 |
| Endpoint-3 FIFO.
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#define | USB_F4 0x400890A0 |
| Endpoint-4 FIFO.
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#define | USB_F5 0x400890A8 |
| Endpoint-5 FIFO.
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#define | USB_OIE_OUTEP5IE 0x00000020 |
| OUT EP5 interrupt enable.
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#define | USB_OIE_OUTEP4IE 0x00000010 |
| OUT EP4 interrupt enable.
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#define | USB_OIE_OUTEP3IE 0x00000008 |
| OUT EP3 interrupt enable.
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#define | USB_OIE_OUTEP2IE 0x00000004 |
| OUT EP2 interrupt enable.
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#define | USB_OIE_OUTEP1IE 0x00000002 |
| OUT EP1 interrupt enable.
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#define | USB_CS0_CLR_SETUP_END 0x00000080 |
| Listed as reserved in the UG, is this right?
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#define | USB_CS0_CSIL_CLR_OUTPKT_RDY_or_CLR_DATA_TOG 0x00000040 |
| Deassert OUTPKT_RDY bit of this register or reset the data toggle to 0.
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#define | USB_CS0_CLR_OUTPKT_RDY 0x00000040 |
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#define | USB_CSIL_CLR_DATA_TOG 0x00000040 |
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#define | USB_CS0_CSIL_SEND_STALL_or_SENT_STALL 0x00000020 |
| Set this bit to 1 to terminate the current transaction or is set when a STALL handshake has been sent.
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#define | USB_CS0_SEND_STALL 0x00000020 |
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#define | USB_CSIL_SENT_STALL 0x00000020 |
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#define | USB_CS0_CSIL_SETUP_END_or_SEND_STALL 0x00000010 |
| Is set if the control transfer ends due to a premature end-of-control transfer or set to 1 to make the USB controller reply with a STALL handshake when receiving IN tokens.
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#define | USB_CS0_SETUP_END 0x00000010 |
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#define | USB_CSIL_SEND_STALL 0x00000010 |
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#define | USB_CS0_CSIL_DATA_END_or_FLUSH_PACKET 0x00000008 |
| Signal the end of a data transfer or set to 1 to flush next packet that is ready to transfer from the IN FIFO.
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#define | USB_CS0_DATA_END 0x00000008 |
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#define | USB_CSIL_FLUSH_PACKET 0x00000008 |
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#define | USB_CS0_CSIL_SENT_STALL_or_UNDERRUN 0x00000004 |
| Set when a STALL handshake is sent or set if an IN token is received when INPKT_RDY = 0, and a zero-length data packet is transmitted in response to the IN token. More...
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#define | USB_CS0_SENT_STALL 0x00000004 |
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#define | USB_CSIL_UNDERRUN 0x00000004 |
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#define | USB_CS0_CSIL_INPKT_RDY_or_PKT_PRESENT 0x00000002 |
| Data packet has been loaded into the EP0 FIFO or at least one packet in the IN FIFO.
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#define | USB_CS0_INPKT_RDY 0x00000002 |
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#define | USB_CSIL_PKT_PRESENT 0x00000002 |
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#define | USB_CS0_CSIL_OUTPKT_RDY_or_INPKT_RDY 0x00000001 |
| Data packet received or data packet has been loaded into the IN FIFO.
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#define | USB_CS0_OUTPKT_RDY 0x00000001 |
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#define | USB_CSIL_INPKT_RDY 0x00000001 |
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#define | USB_CSOL_CLR_DATA_TOG 0x00000080 |
| Setting resets data toggle to 0.
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#define | USB_CSOL_SENT_STALL 0x00000040 |
| STALL handshake sent.
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#define | USB_CSOL_SEND_STALL 0x00000020 |
| Reply with STALL to OUT tokens.
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#define | USB_CSOL_FLUSH_PACKET 0x00000010 |
| Flush next packet read from OUT FIFO.
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#define | USB_CSOL_DATA_ERROR 0x00000008 |
| CRC or bit-stuff error in RX packet.
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#define | USB_CSOL_OVERRUN 0x00000004 |
| OUT packet can not be loaded into OUT FIFO.
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#define | USB_CSOL_FIFO_FULL 0x00000002 |
| OUT FIFO full.
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#define | USB_CSOL_OUTPKT_RDY 0x00000001 |
| OUT packet read in OUT FIFO.
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Driver for the cc2538 USB controller.
We use the USB core in cpu/cc253x/usb which is known to work on Linux as well as on OS X.
#define USB_CS0_CSIL_SENT_STALL_or_UNDERRUN 0x00000004 |
Set when a STALL handshake is sent or set if an IN token is received when INPKT_RDY = 0, and a zero-length data packet is transmitted in response to the IN token.
In bulk/interrupt mode, this bit is set when a NAK is returned in response to an IN token
Definition at line 260 of file usb-regs.h.