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#define | UDMA_STAT 0x400FF000 |
| DMA status.
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#define | UDMA_CFG 0x400FF004 |
| DMA configuration.
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#define | UDMA_CTLBASE 0x400FF008 |
| DMA channel control base pointer.
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#define | UDMA_ALTBASE 0x400FF00C |
| DMA alternate channel control base pointer.
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#define | UDMA_WAITSTAT 0x400FF010 |
| DMA channel wait-on-request status.
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#define | UDMA_SWREQ 0x400FF014 |
| DMA channel software request.
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#define | UDMA_USEBURSTSET 0x400FF018 |
| DMA channel useburst set.
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#define | UDMA_USEBURSTCLR 0x400FF01C |
| DMA channel useburst clear.
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#define | UDMA_REQMASKSET 0x400FF020 |
| DMA channel request mask set.
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#define | UDMA_REQMASKCLR 0x400FF024 |
| DMA channel request mask clear.
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#define | UDMA_ENASET 0x400FF028 |
| DMA channel enable set.
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#define | UDMA_ENACLR 0x400FF02C |
| DMA channel enable clear.
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#define | UDMA_ALTSET 0x400FF030 |
| DMA channel primary alternate set.
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#define | UDMA_ALTCLR 0x400FF034 |
| DMA channel primary alternate clear.
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#define | UDMA_PRIOSET 0x400FF038 |
| DMA channel priority set.
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#define | UDMA_PRIOCLR 0x400FF03C |
| DMA channel priority clear.
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#define | UDMA_ERRCLR 0x400FF04C |
| DMA bus error clear.
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#define | UDMA_CHASGN 0x400FF500 |
| DMA channel assignment.
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#define | UDMA_CHIS 0x400FF504 |
| DMA channel interrupt status.
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#define | UDMA_CHMAP0 0x400FF510 |
| DMA channel map select 0.
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#define | UDMA_CHMAP1 0x400FF514 |
| DMA channel map select 1.
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#define | UDMA_CHMAP2 0x400FF518 |
| DMA channel map select 2.
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#define | UDMA_CHMAP3 0x400FF51C |
| DMA channel map select 3.
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#define | UDMA_CHMAP0_CH7SEL 0xF0000000 |
| uDMA channel 7 source select
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#define | UDMA_CHMAP0_CH6SEL 0x0F000000 |
| uDMA channel 6 source select
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#define | UDMA_CHMAP0_CH5SEL 0x00F00000 |
| uDMA channel 5 source select
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#define | UDMA_CHMAP0_CH4SEL 0x000F0000 |
| uDMA channel 4 source select
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#define | UDMA_CHMAP0_CH3SEL 0x0000F000 |
| uDMA channel 3 source select
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#define | UDMA_CHMAP0_CH2SEL 0x00000F00 |
| uDMA channel 2 source select
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#define | UDMA_CHMAP0_CH1SEL 0x000000F0 |
| uDMA channel 1 source select
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#define | UDMA_CHMAP0_CH0SEL 0x0000000F |
| uDMA channel 0 source select
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#define | UDMA_CHMAP1_CH15SEL 0xF0000000 |
| uDMA channel 15 source select
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#define | UDMA_CHMAP1_CH14SEL 0x0F000000 |
| uDMA channel 14 source select
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#define | UDMA_CHMAP1_CH13SEL 0x00F00000 |
| uDMA channel 13 source select
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#define | UDMA_CHMAP1_CH12SEL 0x000F0000 |
| uDMA channel 12 source select
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#define | UDMA_CHMAP1_CH11SEL 0x0000F000 |
| uDMA channel 11 source select
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#define | UDMA_CHMAP1_CH10SEL 0x00000F00 |
| uDMA channel 10 source select
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#define | UDMA_CHMAP1_CH9SEL 0x000000F0 |
| uDMA channel 9 source select
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#define | UDMA_CHMAP1_CH8SEL 0x0000000F |
| uDMA channel 8 source select
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#define | UDMA_CHMAP2_CH23SEL 0xF0000000 |
| uDMA channel 23 source select
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#define | UDMA_CHMAP2_CH22SEL 0x0F000000 |
| uDMA channel 22 source select
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#define | UDMA_CHMAP2_CH21SEL 0x00F00000 |
| uDMA channel 21 source select
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#define | UDMA_CHMAP2_CH20SEL 0x000F0000 |
| uDMA channel 20 source select
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#define | UDMA_CHMAP2_CH19SEL 0x0000F000 |
| uDMA channel 19 source select
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#define | UDMA_CHMAP2_CH18SEL 0x00000F00 |
| uDMA channel 18 source select
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#define | UDMA_CHMAP2_CH17SEL 0x000000F0 |
| uDMA channel 17 source select
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#define | UDMA_CHMAP2_CH16SEL 0x0000000F |
| uDMA channel 16 source select
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#define | UDMA_CHMAP3_CH31SEL 0xF0000000 |
| uDMA channel 31 source select
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#define | UDMA_CHMAP3_CH30SEL 0x0F000000 |
| uDMA channel 30 source select
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#define | UDMA_CHMAP3_CH29SEL 0x00F00000 |
| uDMA channel 29 source select
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#define | UDMA_CHMAP3_CH28SEL 0x000F0000 |
| uDMA channel 28 source select
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#define | UDMA_CHMAP3_CH27SEL 0x0000F000 |
| uDMA channel 27 source select
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#define | UDMA_CHMAP3_CH26SEL 0x00000F00 |
| uDMA channel 26 source select
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#define | UDMA_CHMAP3_CH25SEL 0x000000F0 |
| uDMA channel 25 source select
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#define | UDMA_CHMAP3_CH24SEL 0x0000000F |
| uDMA channel 24 source select
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udma_set_channel_control_word()
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#define | UDMA_CHCTL_DSTINC_NONE 0xC0000000 |
| Dst address no increment.
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#define | UDMA_CHCTL_DSTINC_32 0x80000000 |
| Dst address increment 32 bit.
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#define | UDMA_CHCTL_DSTINC_16 0x40000000 |
| Dst address increment 16 bit.
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#define | UDMA_CHCTL_DSTINC_8 0x00000000 |
| Dst address increment 8 bit.
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#define | UDMA_CHCTL_DSTSIZE_32 0x20000000 |
| Destination size 32 bit.
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#define | UDMA_CHCTL_DSTSIZE_16 0x10000000 |
| Destination size 16 bit.
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#define | UDMA_CHCTL_DSTSIZE_8 0x00000000 |
| Destination size 8 bit.
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#define | UDMA_CHCTL_SRCINC_NONE 0x0C000000 |
| Source address no increment.
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#define | UDMA_CHCTL_SRCINC_32 0x08000000 |
| Source address increment 32 bit.
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#define | UDMA_CHCTL_SRCINC_16 0x04000000 |
| Source address increment 16 bit.
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#define | UDMA_CHCTL_SRCINC_8 0x00000000 |
| Source address increment 8 bit.
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#define | UDMA_CHCTL_SRCSIZE_32 0x02000000 |
| Source size 32 bit.
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#define | UDMA_CHCTL_SRCSIZE_16 0x01000000 |
| Source size 16 bit.
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#define | UDMA_CHCTL_SRCSIZE_8 0x00000000 |
| Source size 8 bit.
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#define | UDMA_CHCTL_ARBSIZE_1 0x00000000 |
| Arbitration size 1 Transfer.
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#define | UDMA_CHCTL_ARBSIZE_2 0x00004000 |
| Arbitration size 2 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_4 0x00008000 |
| Arbitration size 4 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_8 0x0000C000 |
| Arbitration size 8 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_16 0x00010000 |
| Arbitration size 16 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_32 0x00014000 |
| Arbitration size 32 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_64 0x00018000 |
| Arbitration size 64 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_128 0x0001C000 |
| Arbitration size 128 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_256 0x00020000 |
| Arbitration size 256 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_512 0x00024000 |
| Arbitration size 512 Transfers.
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#define | UDMA_CHCTL_ARBSIZE_1024 0x00028000 |
| Arbitration size 1024 Transfers.
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#define | UDMA_CHCTL_XFERMODE_STOP 0x00000000 |
| Stop.
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#define | UDMA_CHCTL_XFERMODE_BASIC 0x00000001 |
| Basic.
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#define | UDMA_CHCTL_XFERMODE_AUTO 0x00000002 |
| Auto-Request.
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#define | UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 |
| Ping-Pong.
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#define | UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 |
| Memory Scatter-Gather.
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#define | UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 |
| Memory Scatter-Gather Alt.
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#define | UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 |
| Peripheral Scatter-Gather.
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#define | UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 |
| Peripheral Scatter-Gather Alt.
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Driver for the cc2538 uDMA controller.
void udma_set_channel_control_word |
( |
uint8_t |
channel, |
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uint32_t |
ctrl |
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) |
| |
Configure the channel's control word.
- Parameters
-
channel | The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL] |
ctrl | The value of the control word |
The value of the control word is generated by ORing the values defined as UDMA_CHCTL_xyz
For example, to configure a channel with 8 bit source and destination size, 0 source increment and 8 bit destination increment, one would need to pass UDMA_CHCTL_DSTINC_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_DSTSIZE_8
Macros defined as 0 can be omitted.
Definition at line 90 of file udma.c.