38typedef struct spi_locks_s {
44spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKED, NULL } };
48typedef struct board_spi_controller_s {
50 uint32_t power_domain;
52 uint32_t ssi_clkgr_clk_en;
53} board_spi_controller_t;
55static const board_spi_controller_t spi_controller[SPI_CONTROLLER_COUNT] = {
58 .power_domain = PRCM_DOMAIN_SERIAL,
59 .prcm_periph = PRCM_PERIPH_SSI0,
60 .ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI0
64 .power_domain = PRCM_DOMAIN_PERIPH,
65 .prcm_periph = PRCM_PERIPH_SSI1,
66 .ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI1
73 if(board_spi_locks_spi[dev->spi_controller].owner == dev) {
83 if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) {
94 if(dev->spi_pha == 0 && dev->spi_pol == 0) {
95 return SSI_FRF_MOTO_MODE_0;
96 }
else if(dev->spi_pha != 0 && dev->spi_pol == 0) {
97 return SSI_FRF_MOTO_MODE_1;
98 }
else if(dev->spi_pha == 0 && dev->spi_pol != 0) {
99 return SSI_FRF_MOTO_MODE_2;
101 return SSI_FRF_MOTO_MODE_3;
111 if(
mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) ==
false) {
112 return SPI_DEV_STATUS_BUS_LOCKED;
115 board_spi_locks_spi[dev->spi_controller].owner = dev;
118 ti_lib_ioc_pin_type_gpio_output(dev->pin_spi_cs);
121 ti_lib_prcm_power_domain_on(spi_controller[dev->spi_controller].power_domain);
122 while((ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain)
123 != PRCM_DOMAIN_POWER_ON)) ;
126 ti_lib_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph);
127 ti_lib_prcm_load_set();
128 while(!ti_lib_prcm_load_get()) ;
131 ti_lib_ssi_int_disable(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF);
132 ti_lib_ssi_int_clear(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXTO);
134 ti_lib_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base,
135 ti_lib_sys_ctrl_clock_get(),
136 get_mode(dev), SSI_MODE_MASTER,
137 dev->spi_bit_rate, 8);
138 ti_lib_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base,
140 dev->pin_spi_mosi, IOID_UNUSED,
143 ti_lib_ssi_enable(spi_controller[dev->spi_controller].ssi_base);
146 while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
148 return SPI_DEV_STATUS_OK;
155 return SPI_DEV_STATUS_BUS_NOT_OWNED;
159 ti_lib_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph);
160 ti_lib_prcm_load_set();
161 while(!ti_lib_prcm_load_get()) ;
164 ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_miso);
165 ti_lib_ioc_io_port_pull_set(dev->pin_spi_miso, IOC_IOPULL_DOWN);
167 ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_mosi);
168 ti_lib_ioc_io_port_pull_set(dev->pin_spi_mosi, IOC_IOPULL_DOWN);
170 ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_sck);
171 ti_lib_ioc_io_port_pull_set(dev->pin_spi_sck, IOC_IOPULL_DOWN);
174 board_spi_locks_spi[dev->spi_controller].owner = NULL;
175 mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock);
177 return SPI_DEV_STATUS_OK;
182 const uint8_t *write_buf,
int wlen,
183 uint8_t *inbuf,
int rlen,
int ignore_len)
190 return SPI_DEV_STATUS_BUS_NOT_OWNED;
193 if(ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain)
194 != PRCM_DOMAIN_POWER_ON) {
195 return SPI_DEV_STATUS_CLOSED;
199 if(!(HWREG(PRCM_BASE + PRCM_O_SSICLKGR) & spi_controller[dev->spi_controller].ssi_clkgr_clk_en)) {
200 return SPI_DEV_STATUS_CLOSED;
203 totlen = MAX(rlen + ignore_len, wlen);
207 return SPI_DEV_STATUS_OK;
210 for(i = 0; i < totlen; i++) {
211 c = i < wlen ? write_buf[i] : 0;
212 ti_lib_ssi_data_put(spi_controller[dev->spi_controller].ssi_base, (uint8_t)c);
213 ti_lib_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c);
215 inbuf[i] = (uint8_t)c;
218 while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
219 return SPI_DEV_STATUS_OK;
#define SSI1_BASE
Base address for SSI1.
#define SSI0_BASE
Base address for SSI0.
#define mutex_try_lock(m)
Try to lock a mutex.
#define mutex_unlock(m)
Unlock a previously acquired mutex.
spi_status_t spi_arch_close_and_unlock(const spi_device_t *dev)
Closes and unlocks an SPI controller.
spi_status_t spi_arch_transfer(const spi_device_t *dev, const uint8_t *write_buf, int wlen, uint8_t *inbuf, int rlen, int ignore_len)
Performs an SPI transfer.
spi_status_t
SPI return codes.
spi_status_t spi_arch_lock_and_open(const spi_device_t *dev)
Locks and opens an SPI controller to the configuration specified.
bool spi_arch_has_lock(const spi_device_t *dev)
Checks if a device has locked an SPI controller.
bool spi_arch_is_bus_locked(const spi_device_t *dev)
Checks if an SPI controller is locked by any device.
Header file for the SPI HAL.
SPI Device Configuration.
Header file with macros which rename TI CC26xxware functions.