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CMSIS Cortex-M3 core peripheral access layer header file for CC13xx/CC26xx. More...

#include "core_cm3.h"

Go to the source code of this file.

Macros

Processor and Core Peripheral Section
#define __MPU_PRESENT   1
 MPU present or not.
 
#define __NVIC_PRIO_BITS   3
 Number of Bits used for Priority Levels.
 
#define __Vendor_SysTickConfig   0
 Set to 1 if different SysTick Config is used.
 

Interrupt Number Definition

#define SysTick_IRQn   CC13XX_CC26XX_CM3_EXCEPTION_SYS_TICK
 
enum  cc13xx_cc26xx_cm3_irq_e {
  CC13XX_CC26XX_CM3_EXCEPTION_RESET = -15 , CC13XX_CC26XX_CM3_EXCEPTION_NMI = -14 , CC13XX_CC26XX_CM3_EXCEPTION_HARD_FAULT = -13 , CC13XX_CC26XX_CM3_EXCEPTION_MPU_FAULT = -12 ,
  CC13XX_CC26XX_CM3_EXCEPTION_BUS_FAULT = -11 , CC13XX_CC26XX_CM3_EXCEPTION_USAGE_FAULT = -10 , CC13XX_CC26XX_CM3_EXCEPTION_SV_CALL = -5 , CC13XX_CC26XX_CM3_EXCEPTION_DEBUG_MON = -4 ,
  CC13XX_CC26XX_CM3_EXCEPTION_PEND_SV = -2 , CC13XX_CC26XX_CM3_EXCEPTION_SYS_TICK = -1 , CC13XX_CC26XX_CM3_IRQ_EDGE_DETECT = 0 , CC13XX_CC26XX_CM3_EXCEPTION_I2C = 1 ,
  CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE1 = 2 , CC13XX_CC26XX_CM3_EXCEPTION_AON_SPI_SLAVE = 3 , CC13XX_CC26XX_CM3_EXCEPTION_AON_RTC = 4 , CC13XX_CC26XX_CM3_EXCEPTION_UART0 = 5 ,
  CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV0 = 6 , CC13XX_CC26XX_CM3_EXCEPTION_SSI0 = 7 , CC13XX_CC26XX_CM3_EXCEPTION_SSI1 = 8 , CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE0 = 9 ,
  CC13XX_CC26XX_CM3_EXCEPTION_RF_HW = 10 , CC13XX_CC26XX_CM3_EXCEPTION_RF_CMD_ACK = 11 , CC13XX_CC26XX_CM3_EXCEPTION_I2S = 12 , CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV1 = 13 ,
  CC13XX_CC26XX_CM3_EXCEPTION_WATCHDOG = 14 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0A = 15 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0B = 16 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1A = 17 ,
  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1B = 18 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2A = 19 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2B = 20 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3A = 21 ,
  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3B = 22 , CC13XX_CC26XX_CM3_EXCEPTION_CRYPTO = 23 , CC13XX_CC26XX_CM3_EXCEPTION_UDMA = 24 , CC13XX_CC26XX_CM3_EXCEPTION_UDMA_ERR = 25 ,
  CC13XX_CC26XX_CM3_EXCEPTION_FLASH_CTRL = 26 , CC13XX_CC26XX_CM3_EXCEPTION_SW0 = 27 , CC13XX_CC26XX_CM3_EXCEPTION_AUX_COM_EVENT = 28 , CC13XX_CC26XX_CM3_EXCEPTION_AON_PRG0 = 29 ,
  CC13XX_CC26XX_CM3_EXCEPTION_PROG = 30 , CC13XX_CC26XX_CM3_EXCEPTION_AUX_COMPA = 31 , CC13XX_CC26XX_CM3_EXCEPTION_AUX_ADC = 32 , CC13XX_CC26XX_CM3_EXCEPTION_TRNG = 33 ,
  CC13XX_CC26XX_CM3_EXCEPTION_RESET = -15 , CC13XX_CC26XX_CM3_EXCEPTION_NMI = -14 , CC13XX_CC26XX_CM3_EXCEPTION_HARD_FAULT = -13 , CC13XX_CC26XX_CM3_EXCEPTION_MPU_FAULT = -12 ,
  CC13XX_CC26XX_CM3_EXCEPTION_BUS_FAULT = -11 , CC13XX_CC26XX_CM3_EXCEPTION_USAGE_FAULT = -10 , CC13XX_CC26XX_CM3_EXCEPTION_SV_CALL = -5 , CC13XX_CC26XX_CM3_EXCEPTION_DEBUG_MON = -4 ,
  CC13XX_CC26XX_CM3_EXCEPTION_PEND_SV = -2 , CC13XX_CC26XX_CM3_EXCEPTION_SYS_TICK = -1 , CC13XX_CC26XX_CM3_IRQ_EDGE_DETECT = 0 , CC13XX_CC26XX_CM3_EXCEPTION_I2C = 1 ,
  CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE1 = 2 , CC13XX_CC26XX_CM3_EXCEPTION_AON_SPI_SLAVE = 3 , CC13XX_CC26XX_CM3_EXCEPTION_AON_RTC = 4 , CC13XX_CC26XX_CM3_EXCEPTION_UART0 = 5 ,
  CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV0 = 6 , CC13XX_CC26XX_CM3_EXCEPTION_SSI0 = 7 , CC13XX_CC26XX_CM3_EXCEPTION_SSI1 = 8 , CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE0 = 9 ,
  CC13XX_CC26XX_CM3_EXCEPTION_RF_HW = 10 , CC13XX_CC26XX_CM3_EXCEPTION_RF_CMD_ACK = 11 , CC13XX_CC26XX_CM3_EXCEPTION_I2S = 12 , CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV1 = 13 ,
  CC13XX_CC26XX_CM3_EXCEPTION_WATCHDOG = 14 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0A = 15 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0B = 16 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1A = 17 ,
  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1B = 18 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2A = 19 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2B = 20 , CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3A = 21 ,
  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3B = 22 , CC13XX_CC26XX_CM3_EXCEPTION_CRYPTO = 23 , CC13XX_CC26XX_CM3_EXCEPTION_UDMA = 24 , CC13XX_CC26XX_CM3_EXCEPTION_UDMA_ERR = 25 ,
  CC13XX_CC26XX_CM3_EXCEPTION_FLASH_CTRL = 26 , CC13XX_CC26XX_CM3_EXCEPTION_SW0 = 27 , CC13XX_CC26XX_CM3_EXCEPTION_AUX_COM_EVENT = 28 , CC13XX_CC26XX_CM3_EXCEPTION_AON_PRG0 = 29 ,
  CC13XX_CC26XX_CM3_EXCEPTION_PROG = 30 , CC13XX_CC26XX_CM3_EXCEPTION_AUX_COMPA = 31 , CC13XX_CC26XX_CM3_EXCEPTION_AUX_ADC = 32 , CC13XX_CC26XX_CM3_EXCEPTION_TRNG = 33
}
 
typedef enum cc13xx_cc26xx_cm3_irq_e cc13xx_cc26xx_cm3_irq_t
 
typedef cc13xx_cc26xx_cm3_irq_t IRQn_Type
 

Detailed Description

CMSIS Cortex-M3 core peripheral access layer header file for CC13xx/CC26xx.

Definition in file cc13x0-cc26x0-cm3.h.