Contiki-NG
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smartrf-settings.c
1/*
2 * Copyright (c) 2015, Texas Instruments Incorporated - http://www.ti.com/
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the copyright holder nor the names of its
14 * contributors may be used to endorse or promote products derived
15 * from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
20 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
21 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
28 * OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30/*---------------------------------------------------------------------------*/
31#include "contiki.h"
32
33#include "rf-core/dot-15-4g.h"
34#include "driverlib/rf_mailbox.h"
35#include "driverlib/rf_common_cmd.h"
36#include "driverlib/rf_prop_cmd.h"
37
38#include <stdint.h>
39/*---------------------------------------------------------------------------*/
40#ifdef SMARTRF_SETTINGS_CONF_BOARD_OVERRIDES
41#define SMARTRF_SETTINGS_BOARD_OVERRIDES SMARTRF_SETTINGS_CONF_BOARD_OVERRIDES
42#else
43#define SMARTRF_SETTINGS_BOARD_OVERRIDES
44#endif
45/*---------------------------------------------------------------------------*/
46#ifdef SMARTRF_SETTINGS_CONF_BAND_OVERRIDES
47#define SMARTRF_SETTINGS_BAND_OVERRIDES SMARTRF_SETTINGS_CONF_BAND_OVERRIDES
48#else
49#define SMARTRF_SETTINGS_BAND_OVERRIDES
50#endif
51/*---------------------------------------------------------------------------*/
52/* RSSI offset configuration for the 431-527MHz band */
53#ifdef SMARTRF_SETTINGS_CONF_RSSI_OFFSET_431_527
54#define SMARTRF_SETTINGS_RSSI_OFFSET_431_527 SMARTRF_SETTINGS_CONF_RSSI_OFFSET_431_527
55#else
56#define SMARTRF_SETTINGS_RSSI_OFFSET_431_527 0x000288A3
57#endif
58/*---------------------------------------------------------------------------*/
59/* RSSI offset configuration for the 779-930MHz band */
60#ifdef SMARTRF_SETTINGS_CONF_RSSI_OFFSET_779_930
61#define SMARTRF_SETTINGS_RSSI_OFFSET_779_930 SMARTRF_SETTINGS_CONF_RSSI_OFFSET_779_930
62#else
63#define SMARTRF_SETTINGS_RSSI_OFFSET_779_930 0x00FB88A3
64#endif
65/*---------------------------------------------------------------------------*/
66#ifdef SMARTRF_SETTINGS_CONF_OVERRIDE_TRIM_OFFSET
67#define SMARTRF_SETTINGS_OVERRIDE_TRIM_OFFSET SMARTRF_SETTINGS_CONF_OVERRIDE_TRIM_OFFSET
68#else
69#define SMARTRF_SETTINGS_OVERRIDE_TRIM_OFFSET 0x00038883
70#endif
71/*---------------------------------------------------------------------------*/
72/* Select RSSI offset value based on the frequency band */
73#if DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_470
74#define RSSI_OFFSET SMARTRF_SETTINGS_RSSI_OFFSET_431_527
75#else
76#define RSSI_OFFSET SMARTRF_SETTINGS_RSSI_OFFSET_779_930
77#endif
78/*---------------------------------------------------------------------------*/
79/* Overrides for CMD_PROP_RADIO_DIV_SETUP */
80static uint32_t overrides[] =
81{
82 /*
83 * override_use_patch_prop_genfsk.xml
84 * PHY: Use MCE ROM bank 4, RFE RAM patch
85 */
86 MCE_RFE_OVERRIDE(0, 4, 0, 1, 0, 0),
87 /*
88 * override_synth_prop_863_930_div5.xml
89 * Synth: Set recommended RTRIM to 7
90 */
91 HW_REG_OVERRIDE(0x4038, 0x0037),
92 /* Synth: Set Fref to 4 MHz */
93 (uint32_t)0x000684A3,
94 /* Synth: Configure fine calibration setting */
95 HW_REG_OVERRIDE(0x4020, 0x7F00),
96 /* Synth: Configure fine calibration setting */
97 HW_REG_OVERRIDE(0x4064, 0x0040),
98 /* Synth: Configure fine calibration setting */
99 (uint32_t)0xB1070503,
100 /* Synth: Configure fine calibration setting */
101 (uint32_t)0x05330523,
102 /* Synth: Set loop bandwidth after lock to 20 kHz */
103 (uint32_t)0x0A480583,
104 /* Synth: Set loop bandwidth after lock to 20 kHz */
105 (uint32_t)0x7AB80603,
106 /*
107 * Synth: Configure VCO LDO
108 * (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
109 */
110 ADI_REG_OVERRIDE(1, 4, 0x9F),
111 /* Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1) */
112 ADI_HALFREG_OVERRIDE(1, 7, 0x4, 0x4),
113 /* Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering */
114 (uint32_t)0x02010403,
115 /* Synth: Configure extra PLL filtering */
116 (uint32_t)0x00108463,
117 /* Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us) */
118 (uint32_t)0x04B00243,
119 /*
120 * override_phy_rx_aaf_bw_0xd.xml
121 * Rx: Set anti-aliasing filter bandwidth to 0xD
122 * (in ADI0, set IFAMPCTL3[7:4]=0xD)
123 */
124 ADI_HALFREG_OVERRIDE(0, 61, 0xF, 0xD),
125 /*
126 * override_phy_gfsk_rx.xml
127 * Rx: Set LNA bias current trim offset. The board can override this
128 */
129 (uint32_t)SMARTRF_SETTINGS_OVERRIDE_TRIM_OFFSET,
130 /* Rx: Freeze RSSI on sync found event */
131 HW_REG_OVERRIDE(0x6084, 0x35F1),
132 /*
133 * override_phy_gfsk_pa_ramp_agc_reflevel_0x1a.xml
134 * Tx: Enable PA ramping (0x41). Rx: Set AGC reference level to 0x1A.
135 */
136 HW_REG_OVERRIDE(0x6088, 0x411A),
137 /* Tx: Configure PA ramping setting */
138 HW_REG_OVERRIDE(0x608C, 0x8213),
139 /*
140 * Rx: Set RSSI offset to adjust reported RSSI
141 * The board can override this
142 */
143 (uint32_t)RSSI_OFFSET,
144
145 /*
146 * TX power override
147 * Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8)
148 */
149 ADI_REG_OVERRIDE(0, 12, 0xF8),
150
151 /* Overrides for CRC16 functionality */
152 (uint32_t)0x943,
153 (uint32_t)0x963,
154
155 /* Board-specific overrides, if any */
156 SMARTRF_SETTINGS_BOARD_OVERRIDES
157
158 /* Band-specific overrides, if any */
159 SMARTRF_SETTINGS_BAND_OVERRIDES
160
161 (uint32_t)0xFFFFFFFF,
162};
163/*---------------------------------------------------------------------------*/
164/* CMD_PROP_RADIO_DIV_SETUP */
165rfc_CMD_PROP_RADIO_DIV_SETUP_t smartrf_settings_cmd_prop_radio_div_setup =
166{
167 .commandNo = 0x3807,
168 .status = 0x0000,
169 .pNextOp = 0,
170 .startTime = 0x00000000,
171 .startTrigger.triggerType = 0x0,
172 .startTrigger.bEnaCmd = 0x0,
173 .startTrigger.triggerNo = 0x0,
174 .startTrigger.pastTrig = 0x0,
175 .condition.rule = 0x1,
176 .condition.nSkip = 0x0,
177 .modulation.modType = 0x1,
178 .modulation.deviation = 0x64,
179 .symbolRate.preScale = 0xf,
180 .symbolRate.rateWord = 0x8000,
181 .rxBw = 0x24,
182 .preamConf.nPreamBytes = 0x3,
183 .preamConf.preamMode = 0x0,
184 .formatConf.nSwBits = 0x18,
185 .formatConf.bBitReversal = 0x0,
186 .formatConf.bMsbFirst = 0x1,
187 .formatConf.fecMode = 0x0,
188
189 /* 7: .4g mode with dynamic whitening and CRC choice */
190 .formatConf.whitenMode = 0x7,
191 .config.frontEndMode = 0x00, /* Set by the driver */
192 .config.biasMode = 0x00, /* Set by the driver */
193 .config.analogCfgMode = 0x0,
194 .config.bNoFsPowerUp = 0x0,
195 .txPower = 0x00, /* Driver sets correct value */
196 .pRegOverride = overrides,
197 .intFreq = 0x8000,
198 .centerFreq = 868,
199 .loDivider = 0x05,
200};
201/*---------------------------------------------------------------------------*/
202/* CMD_FS */
203rfc_CMD_FS_t smartrf_settings_cmd_fs =
204{
205 .commandNo = 0x0803,
206 .status = 0x0000,
207 .pNextOp = 0,
208 .startTime = 0x00000000,
209 .startTrigger.triggerType = 0x0,
210 .startTrigger.bEnaCmd = 0x0,
211 .startTrigger.triggerNo = 0x0,
212 .startTrigger.pastTrig = 0x0,
213 .condition.rule = 0x1,
214 .condition.nSkip = 0x0,
215 .frequency = 868,
216 .fractFreq = 0x0000,
217 .synthConf.bTxMode = 0x0,
218 .synthConf.refFreq = 0x0,
219 .__dummy0 = 0x00,
220 .__dummy1 = 0x00,
221 .__dummy2 = 0x00,
222 .__dummy3 = 0x0000,
223};
224/*---------------------------------------------------------------------------*/
225/* CMD_PROP_TX_ADV */
226rfc_CMD_PROP_TX_ADV_t smartrf_settings_cmd_prop_tx_adv =
227{
228 .commandNo = 0x3803,
229 .status = 0x0000,
230 .pNextOp = 0,
231 .startTime = 0x00000000,
232 .startTrigger.triggerType = 0x0,
233 .startTrigger.bEnaCmd = 0x0,
234 .startTrigger.triggerNo = 0x0,
235 .startTrigger.pastTrig = 0x0,
236 .condition.rule = 0x1,
237 .condition.nSkip = 0x0,
238 .pktConf.bFsOff = 0x0,
239 .pktConf.bUseCrc = 0x1,
240 .pktConf.bCrcIncSw = 0x0, /* .4g mode */
241 .pktConf.bCrcIncHdr = 0x0, /* .4g mode */
242 .numHdrBits = 0x10 /* 16: .4g mode */,
243 .pktLen = 0x0000,
244 .startConf.bExtTxTrig = 0x0,
245 .startConf.inputMode = 0x0,
246 .startConf.source = 0x0,
247 .preTrigger.triggerType = TRIG_REL_START,
248 .preTrigger.bEnaCmd = 0x0,
249 .preTrigger.triggerNo = 0x0,
250 .preTrigger.pastTrig = 0x1,
251 .preTime = 0x00000000,
252 .syncWord = 0x0055904e,
253 .pPkt = 0,
254};
255/*---------------------------------------------------------------------------*/
256/* CMD_PROP_RX_ADV */
257rfc_CMD_PROP_RX_ADV_t smartrf_settings_cmd_prop_rx_adv =
258{
259 .commandNo = 0x3804,
260 .status = 0x0000,
261 .pNextOp = 0,
262 .startTime = 0x00000000,
263 .startTrigger.triggerType = 0x0,
264 .startTrigger.bEnaCmd = 0x0,
265 .startTrigger.triggerNo = 0x0,
266 .startTrigger.pastTrig = 0x0,
267 .condition.rule = 0x1,
268 .condition.nSkip = 0x0,
269 .pktConf.bFsOff = 0x0,
270 .pktConf.bRepeatOk = 0x1,
271 .pktConf.bRepeatNok = 0x1,
272 .pktConf.bUseCrc = 0x1,
273 .pktConf.bCrcIncSw = 0x0, /* .4g mode */
274 .pktConf.bCrcIncHdr = 0x0, /* .4g mode */
275 .pktConf.endType = 0x0,
276 .pktConf.filterOp = 0x1,
277 .rxConf.bAutoFlushIgnored = 0x1,
278 .rxConf.bAutoFlushCrcErr = 0x1,
279 .rxConf.bIncludeHdr = 0x0,
280 .rxConf.bIncludeCrc = 0x0,
281 .rxConf.bAppendRssi = 0x1,
282 .rxConf.bAppendTimestamp = 0x0,
283 .rxConf.bAppendStatus = 0x1,
284 .syncWord0 = 0x0055904e,
285 .syncWord1 = 0x00000000,
286 .maxPktLen = 0x0000, /* To be populated by the driver. */
287 .hdrConf.numHdrBits = 0x10, /* 16: .4g mode */
288 .hdrConf.lenPos = 0x0, /* .4g mode */
289 .hdrConf.numLenBits = 0x0B, /* 11 = 0x0B .4g mode */
290 .addrConf.addrType = 0x0,
291 .addrConf.addrSize = 0x0,
292 .addrConf.addrPos = 0x0,
293 .addrConf.numAddr = 0x0,
294 .lenOffset = -4, /* .4g mode */
295 .endTrigger.triggerType = TRIG_NEVER,
296 .endTrigger.bEnaCmd = 0x0,
297 .endTrigger.triggerNo = 0x0,
298 .endTrigger.pastTrig = 0x0,
299 .endTime = 0x00000000,
300 .pAddr = 0,
301 .pQueue = 0,
302 .pOutput = 0,
303};
304/*---------------------------------------------------------------------------*/
dot-15-4g.h
Header file with descriptors for the various modes of operation defined in IEEE 802....