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48 #define RADIO_PHY_OVERHEAD 3
50 #define RADIO_BYTE_AIR_TIME 32
53#define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456))
56#define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183))
58#define RADIO_DELAY_BEFORE_DETECT 0
61#define TSCH_CONF_HW_FRAME_FILTERING 0
63#define PLATFORM_HAS_LEDS 1
64#define PLATFORM_HAS_BUTTON 1
65#define PLATFORM_HAS_LIGHT 1
66#define PLATFORM_HAS_BATTERY 1
67#define PLATFORM_HAS_SHT11 1
68#define PLATFORM_HAS_RADIO 1
71#define F_CPU 3900000uL
74#define NETSTACK_CONF_RADIO cc2420_driver
77#define LEDS_PxDIR P5DIR
78#define LEDS_PxOUT P5OUT
79#define LEDS_CONF_RED 0x10
80#define LEDS_CONF_GREEN 0x20
81#define LEDS_CONF_YELLOW 0x40
82#define LEDS_CONF_ALL ((LEDS_CONF_RED) | (LEDS_CONF_GREEN) | (LEDS_CONF_YELLOW))
84#define LEDS_CONF_LEGACY_API 1
87#ifndef DCOSYNCH_CONF_ENABLED
88#define DCOSYNCH_CONF_ENABLED (!(MAC_CONF_WITH_TSCH))
92#ifndef CC2420_CONF_SFD_TIMESTAMPS
93#define CC2420_CONF_SFD_TIMESTAMPS (MAC_CONF_WITH_TSCH)
96#ifndef DCOSYNCH_CONF_PERIOD
97#define DCOSYNCH_CONF_PERIOD 30
100#define ROM_ERASE_UNIT_SIZE 512
101#define XMEM_ERASE_UNIT_SIZE (64*1024L)
104#define CFS_CONF_OFFSET_TYPE long
108#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
111#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
113#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
114#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
116#define CFS_RAM_CONF_SIZE 4096
123#define SPI_TXBUF U0TXBUF
124#define SPI_RXBUF U0RXBUF
127#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
129#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
131#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
147#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
148#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
150#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
151#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
157#define CC2420_CONF_SYMBOL_LOOP_COUNT 800
160#define CC2420_FIFOP_PORT(type) P1##type
161#define CC2420_FIFOP_PIN 0
163#define CC2420_FIFO_PORT(type) P1##type
164#define CC2420_FIFO_PIN 3
166#define CC2420_CCA_PORT(type) P1##type
167#define CC2420_CCA_PIN 4
169#define CC2420_SFD_PORT(type) P4##type
170#define CC2420_SFD_PIN 1
172#define CC2420_CSN_PORT(type) P4##type
173#define CC2420_CSN_PIN 2
175#define CC2420_VREG_PORT(type) P4##type
176#define CC2420_VREG_PIN 5
178#define CC2420_RESET_PORT(type) P4##type
179#define CC2420_RESET_PIN 6
181#define CC2420_IRQ_VECTOR PORT1_VECTOR
184#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
185#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
186#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
187#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
190#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
191#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
194#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
195#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
198#define CC2420_FIFOP_INT_INIT() do { \
199 CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
200 CC2420_CLEAR_FIFOP_INT(); \
204#define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
205#define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
206#define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
214#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
216#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
217#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
220#define STACK_CONF_ORIGIN ((void *)0x3900)