51#define IOC_PA0_SEL 0x400D4000
52#define IOC_PA1_SEL 0x400D4004
53#define IOC_PA2_SEL 0x400D4008
54#define IOC_PA3_SEL 0x400D400C
55#define IOC_PA4_SEL 0x400D4010
56#define IOC_PA5_SEL 0x400D4014
57#define IOC_PA6_SEL 0x400D4018
58#define IOC_PA7_SEL 0x400D401C
59#define IOC_PB0_SEL 0x400D4020
60#define IOC_PB1_SEL 0x400D4024
61#define IOC_PB2_SEL 0x400D4028
62#define IOC_PB3_SEL 0x400D402C
63#define IOC_PB4_SEL 0x400D4030
64#define IOC_PB5_SEL 0x400D4034
65#define IOC_PB6_SEL 0x400D4038
66#define IOC_PB7_SEL 0x400D403C
67#define IOC_PC0_SEL 0x400D4040
68#define IOC_PC1_SEL 0x400D4044
69#define IOC_PC2_SEL 0x400D4048
70#define IOC_PC3_SEL 0x400D404C
71#define IOC_PC4_SEL 0x400D4050
72#define IOC_PC5_SEL 0x400D4054
73#define IOC_PC6_SEL 0x400D4058
74#define IOC_PC7_SEL 0x400D405C
75#define IOC_PD0_SEL 0x400D4060
76#define IOC_PD1_SEL 0x400D4064
77#define IOC_PD2_SEL 0x400D4068
78#define IOC_PD3_SEL 0x400D406C
79#define IOC_PD4_SEL 0x400D4070
80#define IOC_PD5_SEL 0x400D4074
81#define IOC_PD6_SEL 0x400D4078
82#define IOC_PD7_SEL 0x400D407C
88#define IOC_PA0_OVER 0x400D4080
89#define IOC_PA1_OVER 0x400D4084
90#define IOC_PA2_OVER 0x400D4088
91#define IOC_PA3_OVER 0x400D408C
92#define IOC_PA4_OVER 0x400D4090
93#define IOC_PA5_OVER 0x400D4094
94#define IOC_PA6_OVER 0x400D4098
95#define IOC_PA7_OVER 0x400D409C
96#define IOC_PB0_OVER 0x400D40A0
97#define IOC_PB1_OVER 0x400D40A4
98#define IOC_PB2_OVER 0x400D40A8
99#define IOC_PB3_OVER 0x400D40AC
100#define IOC_PB4_OVER 0x400D40B0
101#define IOC_PB5_OVER 0x400D40B4
102#define IOC_PB6_OVER 0x400D40B8
103#define IOC_PB7_OVER 0x400D40BC
104#define IOC_PC0_OVER 0x400D40C0
105#define IOC_PC1_OVER 0x400D40C4
106#define IOC_PC2_OVER 0x400D40C8
107#define IOC_PC3_OVER 0x400D40CC
108#define IOC_PC4_OVER 0x400D40D0
109#define IOC_PC5_OVER 0x400D40D4
110#define IOC_PC6_OVER 0x400D40D8
111#define IOC_PC7_OVER 0x400D40DC
112#define IOC_PD0_OVER 0x400D40E0
113#define IOC_PD1_OVER 0x400D40E4
114#define IOC_PD2_OVER 0x400D40E8
115#define IOC_PD3_OVER 0x400D40EC
116#define IOC_PD4_OVER 0x400D40F0
117#define IOC_PD5_OVER 0x400D40F4
118#define IOC_PD6_OVER 0x400D40F8
119#define IOC_PD7_OVER 0x400D40FC
125#define IOC_UARTRXD_UART0 0x400D4100
126#define IOC_UARTCTS_UART1 0x400D4104
127#define IOC_UARTRXD_UART1 0x400D4108
128#define IOC_CLK_SSI_SSI0 0x400D410C
129#define IOC_SSIRXD_SSI0 0x400D4110
130#define IOC_SSIFSSIN_SSI0 0x400D4114
131#define IOC_CLK_SSIIN_SSI0 0x400D4118
132#define IOC_CLK_SSI_SSI1 0x400D411C
133#define IOC_SSIRXD_SSI1 0x400D4120
134#define IOC_SSIFSSIN_SSI1 0x400D4124
135#define IOC_CLK_SSIIN_SSI1 0x400D4128
136#define IOC_I2CMSSDA 0x400D412C
137#define IOC_I2CMSSCL 0x400D4130
138#define IOC_GPT0OCP1 0x400D4134
139#define IOC_GPT0OCP2 0x400D4138
140#define IOC_GPT1OCP1 0x400D413C
141#define IOC_GPT1OCP2 0x400D4140
142#define IOC_GPT2OCP1 0x400D4144
143#define IOC_GPT2OCP2 0x400D4148
144#define IOC_GPT3OCP1 0x400D414C
145#define IOC_GPT3OCP2 0x400D4150
151#define IOC_OVR_MASK 0x0000000F
152#define IOC_PXX_SEL_MASK 0x0000001F
153#define IOC_INPUT_SEL_MASK 0x0000001F
159#define IOC_INPUT_SEL_PA0 0x00000000
160#define IOC_INPUT_SEL_PA1 0x00000001
161#define IOC_INPUT_SEL_PA2 0x00000002
162#define IOC_INPUT_SEL_PA3 0x00000003
163#define IOC_INPUT_SEL_PA4 0x00000004
164#define IOC_INPUT_SEL_PA5 0x00000005
165#define IOC_INPUT_SEL_PA6 0x00000006
166#define IOC_INPUT_SEL_PA7 0x00000007
167#define IOC_INPUT_SEL_PB0 0x00000008
168#define IOC_INPUT_SEL_PB1 0x00000009
169#define IOC_INPUT_SEL_PB2 0x0000000A
170#define IOC_INPUT_SEL_PB3 0x0000000B
171#define IOC_INPUT_SEL_PB4 0x0000000C
172#define IOC_INPUT_SEL_PB5 0x0000000D
173#define IOC_INPUT_SEL_PB6 0x0000000E
174#define IOC_INPUT_SEL_PB7 0x0000000F
175#define IOC_INPUT_SEL_PC0 0x00000010
176#define IOC_INPUT_SEL_PC1 0x00000011
177#define IOC_INPUT_SEL_PC2 0x00000012
178#define IOC_INPUT_SEL_PC3 0x00000013
179#define IOC_INPUT_SEL_PC4 0x00000014
180#define IOC_INPUT_SEL_PC5 0x00000015
181#define IOC_INPUT_SEL_PC6 0x00000016
182#define IOC_INPUT_SEL_PC7 0x00000017
183#define IOC_INPUT_SEL_PD0 0x00000018
184#define IOC_INPUT_SEL_PD1 0x00000019
185#define IOC_INPUT_SEL_PD2 0x0000001A
186#define IOC_INPUT_SEL_PD3 0x0000001B
187#define IOC_INPUT_SEL_PD4 0x0000001C
188#define IOC_INPUT_SEL_PD5 0x0000001D
189#define IOC_INPUT_SEL_PD6 0x0000001E
190#define IOC_INPUT_SEL_PD7 0x0000001F
196#define IOC_PXX_SEL_UART0_TXD 0x00000000
197#define IOC_PXX_SEL_UART1_RTS 0x00000001
198#define IOC_PXX_SEL_UART1_TXD 0x00000002
199#define IOC_PXX_SEL_SSI0_TXD 0x00000003
200#define IOC_PXX_SEL_SSI0_CLKOUT 0x00000004
201#define IOC_PXX_SEL_SSI0_FSSOUT 0x00000005
202#define IOC_PXX_SEL_SSI0_STXSER_EN 0x00000006
203#define IOC_PXX_SEL_SSI1_TXD 0x00000007
204#define IOC_PXX_SEL_SSI1_CLKOUT 0x00000008
205#define IOC_PXX_SEL_SSI1_FSSOUT 0x00000009
206#define IOC_PXX_SEL_SSI1_STXSER_EN 0x0000000A
207#define IOC_PXX_SEL_I2C_CMSSDA 0x0000000B
208#define IOC_PXX_SEL_I2C_CMSSCL 0x0000000C
209#define IOC_PXX_SEL_GPT0_ICP1 0x0000000D
210#define IOC_PXX_SEL_GPT0_ICP2 0x0000000E
211#define IOC_PXX_SEL_GPT1_ICP1 0x0000000F
212#define IOC_PXX_SEL_GPT1_ICP2 0x00000010
213#define IOC_PXX_SEL_GPT2_ICP1 0x00000011
214#define IOC_PXX_SEL_GPT2_ICP2 0x00000012
215#define IOC_PXX_SEL_GPT3_ICP1 0x00000013
216#define IOC_PXX_SEL_GPT3_ICP2 0x00000014
222#define IOC_OVERRIDE_OE 0x00000008
223#define IOC_OVERRIDE_PUE 0x00000004
224#define IOC_OVERRIDE_PDE 0x00000002
225#define IOC_OVERRIDE_ANA 0x00000001
226#define IOC_OVERRIDE_DIS 0x00000000
250void ioc_set_over(uint8_t port, uint8_t pin, uint8_t over);
277void ioc_set_sel(uint8_t port, uint8_t pin, uint8_t sel);
286#define ioc_input_sel(port, pin) ((port << 3) | pin)
void ioc_set_sel(uint8_t port, uint8_t pin, uint8_t sel)
Function select for Port:Pin.
void ioc_set_over(uint8_t port, uint8_t pin, uint8_t over)
Set Port:Pin override function.
uint32_t ioc_get_over(uint8_t port, uint8_t pin)
Get Port:Pin override function.
void ioc_init()
Initialise the IOC driver.