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#define | RFCORE_FFSM_SRCRESMASK0 0x40088580 |
| Src addr matching result.
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#define | RFCORE_FFSM_SRCRESMASK1 0x40088584 |
| Src addr matching result.
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#define | RFCORE_FFSM_SRCRESMASK2 0x40088588 |
| Src addr matching result.
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#define | RFCORE_FFSM_SRCRESINDEX 0x4008858C |
| Src addr matching result.
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#define | RFCORE_FFSM_SRCEXTPENDEN0 0x40088590 |
| Src addr matching control.
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#define | RFCORE_FFSM_SRCEXTPENDEN1 0x40088594 |
| Src addr matching control.
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#define | RFCORE_FFSM_SRCEXTPENDEN2 0x40088598 |
| Src addr matching control.
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#define | RFCORE_FFSM_SRCSHORTPENDEN0 0x4008859C |
| Src addr matching control.
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#define | RFCORE_FFSM_SRCSHORTPENDEN1 0x400885A0 |
| Src addr matching control.
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#define | RFCORE_FFSM_SRCSHORTPENDEN2 0x400885A4 |
| Src addr matching control.
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#define | RFCORE_FFSM_EXT_ADDR0 0x400885A8 |
| Local address information.
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#define | RFCORE_FFSM_EXT_ADDR1 0x400885AC |
| Local address information.
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#define | RFCORE_FFSM_EXT_ADDR2 0x400885B0 |
| Local address information.
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#define | RFCORE_FFSM_EXT_ADDR3 0x400885B4 |
| Local address information.
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#define | RFCORE_FFSM_EXT_ADDR4 0x400885B8 |
| Local address information.
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#define | RFCORE_FFSM_EXT_ADDR5 0x400885BC |
| Local address information.
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#define | RFCORE_FFSM_EXT_ADDR6 0x400885C0 |
| Local address information.
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#define | RFCORE_FFSM_EXT_ADDR7 0x400885C4 |
| Local address information.
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#define | RFCORE_FFSM_PAN_ID0 0x400885C8 |
| Local address information.
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#define | RFCORE_FFSM_PAN_ID1 0x400885CC |
| Local address information.
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#define | RFCORE_FFSM_SHORT_ADDR0 0x400885D0 |
| Local address information.
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#define | RFCORE_FFSM_SHORT_ADDR1 0x400885D4 |
| Local address information.
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#define | RFCORE_XREG_FRMFILT0 0x40088600 |
| Frame filtering control.
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#define | RFCORE_XREG_FRMFILT1 0x40088604 |
| Frame filtering control.
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#define | RFCORE_XREG_SRCMATCH 0x40088608 |
| Source address matching.
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#define | RFCORE_XREG_SRCSHORTEN0 0x4008860C |
| Short address matching.
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#define | RFCORE_XREG_SRCSHORTEN1 0x40088610 |
| Short address matching.
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#define | RFCORE_XREG_SRCSHORTEN2 0x40088614 |
| Short address matching.
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#define | RFCORE_XREG_SRCEXTEN0 0x40088618 |
| Extended address matching.
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#define | RFCORE_XREG_SRCEXTEN1 0x4008861C |
| Extended address matching.
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#define | RFCORE_XREG_SRCEXTEN2 0x40088620 |
| Extended address matching.
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#define | RFCORE_XREG_FRMCTRL0 0x40088624 |
| Frame handling.
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#define | RFCORE_XREG_FRMCTRL1 0x40088628 |
| Frame handling.
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#define | RFCORE_XREG_RXENABLE 0x4008862C |
| RX enabling.
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#define | RFCORE_XREG_RXMASKSET 0x40088630 |
| RX enabling.
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#define | RFCORE_XREG_RXMASKCLR 0x40088634 |
| RX disabling.
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#define | RFCORE_XREG_FREQTUNE 0x40088638 |
| Crystal oscillator freq tuning.
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#define | RFCORE_XREG_FREQCTRL 0x4008863C |
| Controls the RF frequency.
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#define | RFCORE_XREG_TXPOWER 0x40088640 |
| Controls the output power.
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#define | RFCORE_XREG_TXCTRL 0x40088644 |
| Controls the TX settings.
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#define | RFCORE_XREG_FSMSTAT0 0x40088648 |
| Radio status register.
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#define | RFCORE_XREG_FSMSTAT1 0x4008864C |
| Radio status register.
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#define | RFCORE_XREG_FIFOPCTRL 0x40088650 |
| FIFOP threshold.
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#define | RFCORE_XREG_FSMCTRL 0x40088654 |
| FSM options.
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#define | RFCORE_XREG_CCACTRL0 0x40088658 |
| CCA threshold.
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#define | RFCORE_XREG_CCACTRL1 0x4008865C |
| Other CCA Options.
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#define | RFCORE_XREG_RSSI 0x40088660 |
| RSSI status register.
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#define | RFCORE_XREG_RSSISTAT 0x40088664 |
| RSSI valid status register.
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#define | RFCORE_XREG_RXFIRST 0x40088668 |
| First byte in RX FIFO.
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#define | RFCORE_XREG_RXFIFOCNT 0x4008866C |
| Number of bytes in RX FIFO.
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#define | RFCORE_XREG_TXFIFOCNT 0x40088670 |
| Number of bytes in TX FIFO.
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#define | RFCORE_XREG_RXFIRST_PTR 0x40088674 |
| RX FIFO pointer.
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#define | RFCORE_XREG_RXLAST_PTR 0x40088678 |
| RX FIFO pointer.
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#define | RFCORE_XREG_RXP1_PTR 0x4008867C |
| RX FIFO pointer.
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#define | RFCORE_XREG_RXP2_PTR 0x40088680 |
| RX FIFO pointer.
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#define | RFCORE_XREG_TXFIRST_PTR 0x40088684 |
| TX FIFO pointer.
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#define | RFCORE_XREG_TXLAST_PTR 0x40088688 |
| TX FIFO pointer.
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#define | RFCORE_XREG_RFIRQM0 0x4008868C |
| RF interrupt masks.
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#define | RFCORE_XREG_RFIRQM1 0x40088690 |
| RF interrupt masks.
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#define | RFCORE_XREG_RFERRM 0x40088694 |
| RF error interrupt mask.
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#define | RFCORE_XREG_D18_SPARE_OPAMPMC 0x40088698 |
| Operational amp mode ctrl.
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#define | RFCORE_XREG_RFRND 0x4008869C |
| Random data.
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#define | RFCORE_XREG_MDMCTRL0 0x400886A0 |
| Controls modem.
|
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#define | RFCORE_XREG_MDMCTRL1 0x400886A4 |
| Controls modem.
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#define | RFCORE_XREG_FREQEST 0x400886A8 |
| Estimated RF frequency offset.
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#define | RFCORE_XREG_RXCTRL 0x400886AC |
| Tune receive section.
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#define | RFCORE_XREG_FSCTRL 0x400886B0 |
| Tune frequency synthesizer.
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#define | RFCORE_XREG_FSCAL1 0x400886B8 |
| Tune frequency calibration.
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#define | RFCORE_XREG_FSCAL2 0x400886BC |
| Tune frequency calibration.
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#define | RFCORE_XREG_FSCAL3 0x400886C0 |
| Tune frequency calibration.
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#define | RFCORE_XREG_AGCCTRL0 0x400886C4 |
| AGC dynamic range control.
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#define | RFCORE_XREG_AGCCTRL1 0x400886C8 |
| AGC reference level.
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#define | RFCORE_XREG_AGCCTRL2 0x400886CC |
| AGC gain override.
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#define | RFCORE_XREG_AGCCTRL3 0x400886D0 |
| AGC control.
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#define | RFCORE_XREG_ADCTEST0 0x400886D4 |
| ADC tuning.
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#define | RFCORE_XREG_ADCTEST1 0x400886D8 |
| ADC tuning.
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#define | RFCORE_XREG_ADCTEST2 0x400886DC |
| ADC tuning.
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#define | RFCORE_XREG_MDMTEST0 0x400886E0 |
| Test register for modem.
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#define | RFCORE_XREG_MDMTEST1 0x400886E4 |
| Test Register for Modem.
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#define | RFCORE_XREG_DACTEST0 0x400886E8 |
| DAC override value.
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#define | RFCORE_XREG_DACTEST1 0x400886EC |
| DAC override value.
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#define | RFCORE_XREG_DACTEST2 0x400886F0 |
| DAC test setting.
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#define | RFCORE_XREG_ATEST 0x400886F4 |
| Analog test control.
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#define | RFCORE_XREG_PTEST0 0x400886F8 |
| Override power-down register.
|
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#define | RFCORE_XREG_PTEST1 0x400886FC |
| Override power-down register.
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#define | RFCORE_XREG_CSPPROG0 0x40088700 |
| CSP program.
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#define | RFCORE_XREG_CSPPROG1 0x40088704 |
| CSP program.
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#define | RFCORE_XREG_CSPPROG2 0x40088708 |
| CSP program.
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#define | RFCORE_XREG_CSPPROG3 0x4008870C |
| CSP program.
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#define | RFCORE_XREG_CSPPROG4 0x40088710 |
| CSP program.
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#define | RFCORE_XREG_CSPPROG5 0x40088714 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG6 0x40088718 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG7 0x4008871C |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG8 0x40088720 |
| CSP program.
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#define | RFCORE_XREG_CSPPROG9 0x40088724 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG10 0x40088728 |
| CSP program.
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#define | RFCORE_XREG_CSPPROG11 0x4008872C |
| CSP program.
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#define | RFCORE_XREG_CSPPROG12 0x40088730 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG13 0x40088734 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG14 0x40088738 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG15 0x4008873C |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG16 0x40088740 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG17 0x40088744 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG18 0x40088748 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG19 0x4008874C |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG20 0x40088750 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG21 0x40088754 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG22 0x40088758 |
| CSP program.
|
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#define | RFCORE_XREG_CSPPROG23 0x4008875C |
| CSP program.
|
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#define | RFCORE_XREG_CSPCTRL 0x40088780 |
| CSP control bit.
|
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#define | RFCORE_XREG_CSPSTAT 0x40088784 |
| CSP status register.
|
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#define | RFCORE_XREG_CSPX 0x40088788 |
| CSP X data register.
|
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#define | RFCORE_XREG_CSPY 0x4008878C |
| CSP Y data register.
|
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#define | RFCORE_XREG_CSPZ 0x40088790 |
| CSP Z data register.
|
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#define | RFCORE_XREG_CSPT 0x40088794 |
| CSP T data register.
|
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#define | RFCORE_XREG_RFC_DUTY_CYCLE 0x400887A0 |
| RX duty cycle control.
|
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#define | RFCORE_XREG_RFC_OBS_CTRL0 0x400887AC |
| RF observation mux control.
|
|
#define | RFCORE_XREG_RFC_OBS_CTRL1 0x400887B0 |
| RF observation mux control.
|
|
#define | RFCORE_XREG_RFC_OBS_CTRL2 0x400887B4 |
| RF observation mux control.
|
|
#define | RFCORE_XREG_TXFILTCFG 0x400887E8 |
| TX filter configuration.
|
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Declarations of RF Core registers. Includes SFR, XREG and FFSM