Contiki-NG
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cc1200-const.h
1/*
2 * Copyright (c) 2015, Weptech elektronik GmbH Germany
3 * http://www.weptech.de
4 *
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
22 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
23 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30 * OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * This file is part of the Contiki operating system.
33 */
34
35#ifndef CC1200_CONST_H_
36#define CC1200_CONST_H_
37
38/*---------------------------------------------------------------------------*/
39/* Register addresses exported from SmartRF Studio */
40#define CC1200_IOCFG3 0x0000 /* GPIO3 IO Pin Configuration */
41#define CC1200_IOCFG2 0x0001 /* GPIO2 IO Pin Configuration */
42#define CC1200_IOCFG1 0x0002 /* GPIO1 IO Pin Configuration */
43#define CC1200_IOCFG0 0x0003 /* GPIO0 IO Pin Configuration */
44#define CC1200_SYNC3 0x0004 /* Sync Word Configuration [31:24] */
45#define CC1200_SYNC2 0x0005 /* Sync Word Configuration [23:16] */
46#define CC1200_SYNC1 0x0006 /* Sync Word Configuration [15:8] */
47#define CC1200_SYNC0 0x0007 /* Sync Word Configuration [7:0] */
48#define CC1200_SYNC_CFG1 0x0008 /* Sync Word Detection Configuration Reg. 1 */
49#define CC1200_SYNC_CFG0 0x0009 /* Sync Word Detection Configuration Reg. 0 */
50#define CC1200_DEVIATION_M 0x000A /* Frequency Deviation Configuration */
51#define CC1200_MODCFG_DEV_E 0x000B /* Modulation Format and Frequency Deviation Configur.. */
52#define CC1200_DCFILT_CFG 0x000C /* Digital DC Removal Configuration */
53#define CC1200_PREAMBLE_CFG1 0x000D /* Preamble Length Configuration Reg. 1 */
54#define CC1200_PREAMBLE_CFG0 0x000E /* Preamble Detection Configuration Reg. 0 */
55#define CC1200_IQIC 0x000F /* Digital Image Channel Compensation Configuration */
56#define CC1200_CHAN_BW 0x0010 /* Channel Filter Configuration */
57#define CC1200_MDMCFG1 0x0011 /* General Modem Parameter Configuration Reg. 1 */
58#define CC1200_MDMCFG0 0x0012 /* General Modem Parameter Configuration Reg. 0 */
59#define CC1200_SYMBOL_RATE2 0x0013 /* Symbol Rate Configuration Exponent and Mantissa [1.. */
60#define CC1200_SYMBOL_RATE1 0x0014 /* Symbol Rate Configuration Mantissa [15:8] */
61#define CC1200_SYMBOL_RATE0 0x0015 /* Symbol Rate Configuration Mantissa [7:0] */
62#define CC1200_AGC_REF 0x0016 /* AGC Reference Level Configuration */
63#define CC1200_AGC_CS_THR 0x0017 /* Carrier Sense Threshold Configuration */
64#define CC1200_AGC_GAIN_ADJUST 0x0018 /* RSSI Offset Configuration */
65#define CC1200_AGC_CFG3 0x0019 /* Automatic Gain Control Configuration Reg. 3 */
66#define CC1200_AGC_CFG2 0x001A /* Automatic Gain Control Configuration Reg. 2 */
67#define CC1200_AGC_CFG1 0x001B /* Automatic Gain Control Configuration Reg. 1 */
68#define CC1200_AGC_CFG0 0x001C /* Automatic Gain Control Configuration Reg. 0 */
69#define CC1200_FIFO_CFG 0x001D /* FIFO Configuration */
70#define CC1200_DEV_ADDR 0x001E /* Device Address Configuration */
71#define CC1200_SETTLING_CFG 0x001F /* Frequency Synthesizer Calibration and Settling Con.. */
72#define CC1200_FS_CFG 0x0020 /* Frequency Synthesizer Configuration */
73#define CC1200_WOR_CFG1 0x0021 /* eWOR Configuration Reg. 1 */
74#define CC1200_WOR_CFG0 0x0022 /* eWOR Configuration Reg. 0 */
75#define CC1200_WOR_EVENT0_MSB 0x0023 /* Event 0 Configuration MSB */
76#define CC1200_WOR_EVENT0_LSB 0x0024 /* Event 0 Configuration LSB */
77#define CC1200_RXDCM_TIME 0x0025 /* RX Duty Cycle Mode Configuration */
78#define CC1200_PKT_CFG2 0x0026 /* Packet Configuration Reg. 2 */
79#define CC1200_PKT_CFG1 0x0027 /* Packet Configuration Reg. 1 */
80#define CC1200_PKT_CFG0 0x0028 /* Packet Configuration Reg. 0 */
81#define CC1200_RFEND_CFG1 0x0029 /* RFEND Configuration Reg. 1 */
82#define CC1200_RFEND_CFG0 0x002A /* RFEND Configuration Reg. 0 */
83#define CC1200_PA_CFG1 0x002B /* Power Amplifier Configuration Reg. 1 */
84#define CC1200_PA_CFG0 0x002C /* Power Amplifier Configuration Reg. 0 */
85#define CC1200_ASK_CFG 0x002D /* ASK Configuration */
86#define CC1200_PKT_LEN 0x002E /* Packet Length Configuration */
87#define CC1200_IF_MIX_CFG 0x2F00 /* IF Mix Configuration */
88#define CC1200_FREQOFF_CFG 0x2F01 /* Frequency Offset Correction Configuration */
89#define CC1200_TOC_CFG 0x2F02 /* Timing Offset Correction Configuration */
90#define CC1200_MARC_SPARE 0x2F03 /* MARC Spare */
91#define CC1200_ECG_CFG 0x2F04 /* External Clock Frequency Configuration */
92#define CC1200_MDMCFG2 0x2F05 /* General Modem Parameter Configuration Reg. 2 */
93#define CC1200_EXT_CTRL 0x2F06 /* External Control Configuration */
94#define CC1200_RCCAL_FINE 0x2F07 /* RC Oscillator Calibration Fine */
95#define CC1200_RCCAL_COARSE 0x2F08 /* RC Oscillator Calibration Coarse */
96#define CC1200_RCCAL_OFFSET 0x2F09 /* RC Oscillator Calibration Clock Offset */
97#define CC1200_FREQOFF1 0x2F0A /* Frequency Offset MSB */
98#define CC1200_FREQOFF0 0x2F0B /* Frequency Offset LSB */
99#define CC1200_FREQ2 0x2F0C /* Frequency Configuration [23:16] */
100#define CC1200_FREQ1 0x2F0D /* Frequency Configuration [15:8] */
101#define CC1200_FREQ0 0x2F0E /* Frequency Configuration [7:0] */
102#define CC1200_IF_ADC2 0x2F0F /* Analog to Digital Converter Configuration Reg. 2 */
103#define CC1200_IF_ADC1 0x2F10 /* Analog to Digital Converter Configuration Reg. 1 */
104#define CC1200_IF_ADC0 0x2F11 /* Analog to Digital Converter Configuration Reg. 0 */
105#define CC1200_FS_DIG1 0x2F12 /* Frequency Synthesizer Digital Reg. 1 */
106#define CC1200_FS_DIG0 0x2F13 /* Frequency Synthesizer Digital Reg. 0 */
107#define CC1200_FS_CAL3 0x2F14 /* Frequency Synthesizer Calibration Reg. 3 */
108#define CC1200_FS_CAL2 0x2F15 /* Frequency Synthesizer Calibration Reg. 2 */
109#define CC1200_FS_CAL1 0x2F16 /* Frequency Synthesizer Calibration Reg. 1 */
110#define CC1200_FS_CAL0 0x2F17 /* Frequency Synthesizer Calibration Reg. 0 */
111#define CC1200_FS_CHP 0x2F18 /* Frequency Synthesizer Charge Pump Configuration */
112#define CC1200_FS_DIVTWO 0x2F19 /* Frequency Synthesizer Divide by 2 */
113#define CC1200_FS_DSM1 0x2F1A /* FS Digital Synthesizer Module Configuration Reg. 1 */
114#define CC1200_FS_DSM0 0x2F1B /* FS Digital Synthesizer Module Configuration Reg. 0 */
115#define CC1200_FS_DVC1 0x2F1C /* Frequency Synthesizer Divider Chain Configuration .. */
116#define CC1200_FS_DVC0 0x2F1D /* Frequency Synthesizer Divider Chain Configuration .. */
117#define CC1200_FS_LBI 0x2F1E /* Frequency Synthesizer Local Bias Configuration */
118#define CC1200_FS_PFD 0x2F1F /* Frequency Synthesizer Phase Frequency Detector Con.. */
119#define CC1200_FS_PRE 0x2F20 /* Frequency Synthesizer Prescaler Configuration */
120#define CC1200_FS_REG_DIV_CML 0x2F21 /* Frequency Synthesizer Divider Regulator Configurat.. */
121#define CC1200_FS_SPARE 0x2F22 /* Frequency Synthesizer Spare */
122#define CC1200_FS_VCO4 0x2F23 /* FS Voltage Controlled Oscillator Configuration Reg.. */
123#define CC1200_FS_VCO3 0x2F24 /* FS Voltage Controlled Oscillator Configuration Reg.. */
124#define CC1200_FS_VCO2 0x2F25 /* FS Voltage Controlled Oscillator Configuration Reg.. */
125#define CC1200_FS_VCO1 0x2F26 /* FS Voltage Controlled Oscillator Configuration Reg.. */
126#define CC1200_FS_VCO0 0x2F27 /* FS Voltage Controlled Oscillator Configuration Reg.. */
127#define CC1200_GBIAS6 0x2F28 /* Global Bias Configuration Reg. 6 */
128#define CC1200_GBIAS5 0x2F29 /* Global Bias Configuration Reg. 5 */
129#define CC1200_GBIAS4 0x2F2A /* Global Bias Configuration Reg. 4 */
130#define CC1200_GBIAS3 0x2F2B /* Global Bias Configuration Reg. 3 */
131#define CC1200_GBIAS2 0x2F2C /* Global Bias Configuration Reg. 2 */
132#define CC1200_GBIAS1 0x2F2D /* Global Bias Configuration Reg. 1 */
133#define CC1200_GBIAS0 0x2F2E /* Global Bias Configuration Reg. 0 */
134#define CC1200_IFAMP 0x2F2F /* Intermediate Frequency Amplifier Configuration */
135#define CC1200_LNA 0x2F30 /* Low Noise Amplifier Configuration */
136#define CC1200_RXMIX 0x2F31 /* RX Mixer Configuration */
137#define CC1200_XOSC5 0x2F32 /* Crystal Oscillator Configuration Reg. 5 */
138#define CC1200_XOSC4 0x2F33 /* Crystal Oscillator Configuration Reg. 4 */
139#define CC1200_XOSC3 0x2F34 /* Crystal Oscillator Configuration Reg. 3 */
140#define CC1200_XOSC2 0x2F35 /* Crystal Oscillator Configuration Reg. 2 */
141#define CC1200_XOSC1 0x2F36 /* Crystal Oscillator Configuration Reg. 1 */
142#define CC1200_XOSC0 0x2F37 /* Crystal Oscillator Configuration Reg. 0 */
143#define CC1200_ANALOG_SPARE 0x2F38 /* Analog Spare */
144#define CC1200_PA_CFG3 0x2F39 /* Power Amplifier Configuration Reg. 3 */
145#define CC1200_WOR_TIME1 0x2F64 /* eWOR Timer Counter Value MSB */
146#define CC1200_WOR_TIME0 0x2F65 /* eWOR Timer Counter Value LSB */
147#define CC1200_WOR_CAPTURE1 0x2F66 /* eWOR Timer Capture Value MSB */
148#define CC1200_WOR_CAPTURE0 0x2F67 /* eWOR Timer Capture Value LSB */
149#define CC1200_BIST 0x2F68 /* MARC Built-In Self-Test */
150#define CC1200_DCFILTOFFSET_I1 0x2F69 /* DC Filter Offset I MSB */
151#define CC1200_DCFILTOFFSET_I0 0x2F6A /* DC Filter Offset I LSB */
152#define CC1200_DCFILTOFFSET_Q1 0x2F6B /* DC Filter Offset Q MSB */
153#define CC1200_DCFILTOFFSET_Q0 0x2F6C /* DC Filter Offset Q LSB */
154#define CC1200_IQIE_I1 0x2F6D /* IQ Imbalance Value I MSB */
155#define CC1200_IQIE_I0 0x2F6E /* IQ Imbalance Value I LSB */
156#define CC1200_IQIE_Q1 0x2F6F /* IQ Imbalance Value Q MSB */
157#define CC1200_IQIE_Q0 0x2F70 /* IQ Imbalance Value Q LSB */
158#define CC1200_RSSI1 0x2F71 /* Received Signal Strength Indicator Reg. 1 */
159#define CC1200_RSSI0 0x2F72 /* Received Signal Strength Indicator Reg.0 */
160#define CC1200_MARCSTATE 0x2F73 /* MARC State */
161#define CC1200_LQI_VAL 0x2F74 /* Link Quality Indicator Value */
162#define CC1200_PQT_SYNC_ERR 0x2F75 /* Preamble and Sync Word Error */
163#define CC1200_DEM_STATUS 0x2F76 /* Demodulator Status */
164#define CC1200_FREQOFF_EST1 0x2F77 /* Frequency Offset Estimate MSB */
165#define CC1200_FREQOFF_EST0 0x2F78 /* Frequency Offset Estimate LSB */
166#define CC1200_AGC_GAIN3 0x2F79 /* Automatic Gain Control Reg. 3 */
167#define CC1200_AGC_GAIN2 0x2F7A /* Automatic Gain Control Reg. 2 */
168#define CC1200_AGC_GAIN1 0x2F7B /* Automatic Gain Control Reg. 1 */
169#define CC1200_AGC_GAIN0 0x2F7C /* Automatic Gain Control Reg. 0 */
170#define CC1200_CFM_RX_DATA_OUT 0x2F7D /* Custom Frequency Modulation RX Data */
171#define CC1200_CFM_TX_DATA_IN 0x2F7E /* Custom Frequency Modulation TX Data */
172#define CC1200_ASK_SOFT_RX_DATA 0x2F7F /* ASK Soft Decision Output */
173#define CC1200_RNDGEN 0x2F80 /* Random Number Generator Value */
174#define CC1200_MAGN2 0x2F81 /* Signal Magnitude after CORDIC [16] */
175#define CC1200_MAGN1 0x2F82 /* Signal Magnitude after CORDIC [15:8] */
176#define CC1200_MAGN0 0x2F83 /* Signal Magnitude after CORDIC [7:0] */
177#define CC1200_ANG1 0x2F84 /* Signal Angular after CORDIC [9:8] */
178#define CC1200_ANG0 0x2F85 /* Signal Angular after CORDIC [7:0] */
179#define CC1200_CHFILT_I2 0x2F86 /* Channel Filter Data Real Part [16] */
180#define CC1200_CHFILT_I1 0x2F87 /* Channel Filter Data Real Part [15:8] */
181#define CC1200_CHFILT_I0 0x2F88 /* Channel Filter Data Real Part [7:0] */
182#define CC1200_CHFILT_Q2 0x2F89 /* Channel Filter Data Imaginary Part [16] */
183#define CC1200_CHFILT_Q1 0x2F8A /* Channel Filter Data Imaginary Part [15:8] */
184#define CC1200_CHFILT_Q0 0x2F8B /* Channel Filter Data Imaginary Part [7:0] */
185#define CC1200_GPIO_STATUS 0x2F8C /* General Purpose Input/Output Status */
186#define CC1200_FSCAL_CTRL 0x2F8D /* Frequency Synthesizer Calibration Control */
187#define CC1200_PHASE_ADJUST 0x2F8E /* Frequency Synthesizer Phase Adjust */
188#define CC1200_PARTNUMBER 0x2F8F /* Part Number */
189#define CC1200_PARTVERSION 0x2F90 /* Part Revision */
190#define CC1200_SERIAL_STATUS 0x2F91 /* Serial Status */
191#define CC1200_MODEM_STATUS1 0x2F92 /* Modem Status Reg. 1 */
192#define CC1200_MODEM_STATUS0 0x2F93 /* Modem Status Reg. 0 */
193#define CC1200_MARC_STATUS1 0x2F94 /* MARC Status Reg. 1 */
194#define CC1200_MARC_STATUS0 0x2F95 /* MARC Status Reg. 0 */
195#define CC1200_PA_IFAMP_TEST 0x2F96 /* Power Amplifier Intermediate Frequency Amplifier T.. */
196#define CC1200_FSRF_TEST 0x2F97 /* Frequency Synthesizer Test */
197#define CC1200_PRE_TEST 0x2F98 /* Frequency Synthesizer Prescaler Test */
198#define CC1200_PRE_OVR 0x2F99 /* Frequency Synthesizer Prescaler Override */
199#define CC1200_ADC_TEST 0x2F9A /* Analog to Digital Converter Test */
200#define CC1200_DVC_TEST 0x2F9B /* Digital Divider Chain Test */
201#define CC1200_ATEST 0x2F9C /* Analog Test */
202#define CC1200_ATEST_LVDS 0x2F9D /* Analog Test LVDS */
203#define CC1200_ATEST_MODE 0x2F9E /* Analog Test Mode */
204#define CC1200_XOSC_TEST1 0x2F9F /* Crystal Oscillator Test Reg. 1 */
205#define CC1200_XOSC_TEST0 0x2FA0 /* Crystal Oscillator Test Reg. 0 */
206#define CC1200_AES 0x2FA1 /* AES */
207#define CC1200_MDM_TEST 0x2FA2 /* MODEM Test */
208#define CC1200_RXFIRST 0x2FD2 /* RX FIFO Pointer First Entry */
209#define CC1200_TXFIRST 0x2FD3 /* TX FIFO Pointer First Entry */
210#define CC1200_RXLAST 0x2FD4 /* RX FIFO Pointer Last Entry */
211#define CC1200_TXLAST 0x2FD5 /* TX FIFO Pointer Last Entry */
212#define CC1200_NUM_TXBYTES 0x2FD6 /* TX FIFO Status */
213#define CC1200_NUM_RXBYTES 0x2FD7 /* RX FIFO Status */
214#define CC1200_FIFO_NUM_TXBYTES 0x2FD8 /* TX FIFO Status */
215#define CC1200_FIFO_NUM_RXBYTES 0x2FD9 /* RX FIFO Status */
216#define CC1200_RXFIFO_PRE_BUF 0x2FDA /* RX FIFO Status */
217#define CC1200_AES_KEY15 0x2FE0 /* Advanced Encryption Standard Key [127:120] */
218#define CC1200_AES_KEY14 0x2FE1 /* Advanced Encryption Standard Key [119:112] */
219#define CC1200_AES_KEY13 0x2FE2 /* Advanced Encryption Standard Key [111:104] */
220#define CC1200_AES_KEY12 0x2FE3 /* Advanced Encryption Standard Key [103:96] */
221#define CC1200_AES_KEY11 0x2FE4 /* Advanced Encryption Standard Key [95:88] */
222#define CC1200_AES_KEY10 0x2FE5 /* Advanced Encryption Standard Key [87:80] */
223#define CC1200_AES_KEY9 0x2FE6 /* Advanced Encryption Standard Key [79:72] */
224#define CC1200_AES_KEY8 0x2FE7 /* Advanced Encryption Standard Key [71:64] */
225#define CC1200_AES_KEY7 0x2FE8 /* Advanced Encryption Standard Key [63:56] */
226#define CC1200_AES_KEY6 0x2FE9 /* Advanced Encryption Standard Key [55:48] */
227#define CC1200_AES_KEY5 0x2FEA /* Advanced Encryption Standard Key [47:40] */
228#define CC1200_AES_KEY4 0x2FEB /* Advanced Encryption Standard Key [39:32] */
229#define CC1200_AES_KEY3 0x2FEC /* Advanced Encryption Standard Key [31:24] */
230#define CC1200_AES_KEY2 0x2FED /* Advanced Encryption Standard Key [23:16] */
231#define CC1200_AES_KEY1 0x2FEE /* Advanced Encryption Standard Key [15:8] */
232#define CC1200_AES_KEY0 0x2FEF /* Advanced Encryption Standard Key [7:0] */
233#define CC1200_AES_BUFFER15 0x2FF0 /* Advanced Encryption Standard Buffer [127:120] */
234#define CC1200_AES_BUFFER14 0x2FF1 /* Advanced Encryption Standard Buffer [119:112] */
235#define CC1200_AES_BUFFER13 0x2FF2 /* Advanced Encryption Standard Buffer [111:104] */
236#define CC1200_AES_BUFFER12 0x2FF3 /* Advanced Encryption Standard Buffer [103:93] */
237#define CC1200_AES_BUFFER11 0x2FF4 /* Advanced Encryption Standard Buffer [95:88] */
238#define CC1200_AES_BUFFER10 0x2FF5 /* Advanced Encryption Standard Buffer [87:80] */
239#define CC1200_AES_BUFFER9 0x2FF6 /* Advanced Encryption Standard Buffer [79:72] */
240#define CC1200_AES_BUFFER8 0x2FF7 /* Advanced Encryption Standard Buffer [71:64] */
241#define CC1200_AES_BUFFER7 0x2FF8 /* Advanced Encryption Standard Buffer [63:56] */
242#define CC1200_AES_BUFFER6 0x2FF9 /* Advanced Encryption Standard Buffer [55:48] */
243#define CC1200_AES_BUFFER5 0x2FFA /* Advanced Encryption Standard Buffer [47:40] */
244#define CC1200_AES_BUFFER4 0x2FFB /* Advanced Encryption Standard Buffer [39:32] */
245#define CC1200_AES_BUFFER3 0x2FFC /* Advanced Encryption Standard Buffer [31:24] */
246#define CC1200_AES_BUFFER2 0x2FFD /* Advanced Encryption Standard Buffer [23:16] */
247#define CC1200_AES_BUFFER1 0x2FFE /* Advanced Encryption Standard Buffer [15:8] */
248#define CC1200_AES_BUFFER0 0x2FFF /* Advanced Encryption Standard Buffer [7:0] */
249/*---------------------------------------------------------------------------*/
250/* Access to RX / TX FIFO */
251#define CC1200_TXFIFO 0x3F
252#define CC1200_RXFIFO 0x3F
253/*---------------------------------------------------------------------------*/
254/* MARC_STATE */
255#define CC1200_MARC_STATE_SLEEP 0x00
256#define CC1200_MARC_STATE_IDLE 0x01
257#define CC1200_MARC_STATE_RX 0x0D
258#define CC1200_MARC_STATE_RX_FIFO_ERR 0x11
259#define CC1200_MARC_STATE_TX 0x13
260#define CC1200_MARC_STATE_TX_FIFO_ERR 0x16
261/*---------------------------------------------------------------------------*/
262/* Status byte */
263#define CC1200_STATUS_BYTE_IDLE (0 << 4)
264#define CC1200_STATUS_BYTE_RX (1 << 4)
265#define CC1200_STATUS_BYTE_TX (2 << 4)
266#define CC1200_STATUS_BYTE_FSTXON (3 << 4)
267#define CC1200_STATUS_BYTE_CALIBRATE (4 << 4)
268#define CC1200_STATUS_BYTE_SETTLING (5 << 4)
269#define CC1200_STATUS_BYTE_RX_FIFO_ERR (6 << 4)
270#define CC1200_STATUS_BYTE_TX_FIFO_ERR (7 << 4)
271/*---------------------------------------------------------------------------*/
272/* GPIO configuration */
273#define CC1200_IOCFG_RXFIFO_THR 0
274#define CC1200_IOCFG_RXFFIFO_THR_PKT 1
275#define CC1200_IOCFG_TXFIFO_THR 2
276#define CC1200_IOCFG_PKT_SYNC_RXTX 6
277#define CC1200_IOCFG_SERIAL_CLK 8
278#define CC1200_IOCFG_SERIAL_RX 9
279#define CC1200_IOCFG_CARRIER_SENSE 17
280#define CC1200_IOCFG_MARC_2PIN_STATUS_1 37
281#define CC1200_IOCFG_MARC_2PIN_STATUS_0 38
282#define CC1200_IOCFG_RXFIFO_CHIP_RDY_N 50
283/*---------------------------------------------------------------------------*/
284/* Command strobes */
285#define CC1200_SRES 0x30
286#define CC1200_SFSTXON 0x31
287#define CC1200_SXOFF 0x32
288#define CC1200_SCAL 0x33
289#define CC1200_SRX 0x34
290#define CC1200_STX 0x35
291#define CC1200_SIDLE 0x36
292#define CC1200_SPWD 0x39
293#define CC1200_SFRX 0x3A
294#define CC1200_SFTX 0x3B
295#define CC1200_SNOP 0x3D
296/*---------------------------------------------------------------------------*/
297/* SPI access modifier */
298#define CC1200_WRITE_BIT 0x00
299#define CC1200_READ_BIT 0x80
300#define CC1200_BURST_BIT 0x40
301#define CC1200_EXTENDED_WRITE_CMD (0x2F | CC1200_WRITE_BIT)
302#define CC1200_EXTENDED_BURST_WRITE_CMD \
303 (0x2F | CC1200_BURST_BIT | CC1200_WRITE_BIT)
304#define CC1200_EXTENDED_READ_CMD (0x2F | CC1200_READ_BIT)
305#define CC1200_EXTENDED_BURST_READ_CMD \
306 (0x2F | CC1200_BURST_BIT | CC1200_READ_BIT)
307/*---------------------------------------------------------------------------*/
308#define CC1200_IS_EXTENDED_ADDR(x) (x & 0x2F00)
309/*---------------------------------------------------------------------------*/
310/* RSSI0 register */
311#define CC1200_CARRIER_SENSE_VALID (1 << 1)
312#define CC1200_CARRIER_SENSE (1 << 2)
313/*---------------------------------------------------------------------------*/
314/* MODEM_STATUS1 register */
315#define CC1200_SYNC_FOUND (1 << 7)
316#define CC1200_PQT_REACHED (1 << 1)
317/*---------------------------------------------------------------------------*/
318#define CC1200_FIFO_SIZE 128
319/*---------------------------------------------------------------------------*/
320/* Output power in dBm */
321/* Up to now we don't handle the special power levels PA_POWER_RAMP < 3, hence
322 * the minimum tx power is -16. See update_txpower().
323 */
324#define CC1200_CONST_TX_POWER_MIN (-16)
325/*
326 * Maximum output power will propably depend on the band we use due to
327 * regulation issues
328 */
329#define CC1200_CONST_TX_POWER_MAX 14
330/*---------------------------------------------------------------------------*/
331/* CCA threshold in dBm */
332#define CC1200_CONST_CCA_THRESHOLD_MIN (-127)
333#define CC1200_CONST_CCA_THRESHOLD_MAX 127
334
335#endif /* CC1200_CONST_H_ */