56 uint32_t aes_key_store_size;
58 uint64_t aligned_keys[AES_KEY_AREAS * 128 / 8 /
sizeof(uint64_t)];
62 return CRYPTO_RESOURCE_IN_USE;
67 for(i = 0; i <
count; i++) {
68 rom_util_memcpy(&aligned_keys[i << 2], &((
const uint64_t *)keys)[i * 3],
70 aligned_keys[(i << 2) + 3] = 0;
81 rom_util_memcpy(aligned_keys, keys,
count << 4);
101 ~AES_KEY_STORE_SIZE_KEY_SIZE_M) | key_size;
105 areas = ((0x00000001 <<
count) - 1) << start_area;
120 ~AES_DMAC_CH_DMALENGTH_DMALEN_M) |
134 return CRYPTO_DMA_BUS_ERROR;
140 return AES_KEYSTORE_WRITE_ERROR;
152 return AES_KEYSTORE_WRITE_ERROR;
155 return CRYPTO_SUCCESS;
160 const void *adata, uint16_t adata_len,
161 const void *data_in,
void *data_out, uint16_t data_len,
162 struct process *process)
165 return CRYPTO_RESOURCE_IN_USE;
188 return AES_KEYSTORE_READ_ERROR;
230 return CRYPTO_DMA_BUS_ERROR;
241 if(process != NULL) {
256 if(data_out != NULL) {
266 return CRYPTO_SUCCESS;
280 uint32_t aes_ctrl_int_stat;
295 return CRYPTO_DMA_BUS_ERROR;
298 return AES_KEYSTORE_WRITE_ERROR;
301 return AES_KEYSTORE_READ_ERROR;
304 if(iv != NULL || tag != NULL) {
330 return CRYPTO_SUCCESS;
Header file for the cc2538 AES driver.
#define AES_CTRL_INT_CLR
Interrupt clear.
#define AES_AES_IV_0
AES initialization vector.
#define AES_AES_CTRL_SAVED_CONTEXT_READY
AES auth.
#define AES_KEY_STORE_SIZE_KEY_SIZE_128
Key size: 128 bits.
#define AES_CTRL_INT_CLR_DMA_BUS_ERR
Clear DMA bus error status.
#define AES_DMAC_CH1_CTRL
Channel 1 control.
#define AES_CTRL_INT_CFG
Interrupt configuration.
#define AES_AES_TAG_OUT_2
TAG.
#define AES_CTRL_INT_CFG_LEVEL
Level interrupt type.
#define AES_DMAC_CH1_DMALENGTH
Channel 1 DMA length.
#define AES_AES_IV_3
AES initialization vector.
#define AES_CTRL_INT_STAT_KEY_ST_WR_ERR
Write error detected.
#define AES_KEY_STORE_SIZE
Key store size.
#define AES_CTRL_INT_EN_DMA_IN_DONE
DMA input done interrupt enabled.
#define AES_AES_CTRL
AES input/output buffer control and mode.
#define AES_KEY_STORE_SIZE_KEY_SIZE_M
Key size mask.
#define AES_CTRL_INT_STAT_KEY_ST_RD_ERR
Read error detected.
#define AES_KEY_STORE_WRITTEN_AREA
Key store written area.
#define AES_CTRL_INT_STAT_DMA_BUS_ERR
DMA bus error detected.
uint8_t aes_load_keys(const void *keys, uint8_t key_size, uint8_t count, uint8_t start_area)
Writes keys into the Key RAM.
uint8_t aes_auth_crypt_check_status(void)
Checks the status of the AES authentication/crypto operation.
#define AES_AES_AUTH_LENGTH
Authentication length.
#define AES_AES_CTRL_GCM
AES-GCM mode.
#define AES_AES_CTRL_CCM
AES-CCM mode.
#define AES_DMAC_CH0_CTRL
Channel 0 control.
#define AES_DMAC_CH_CTRL_EN
Channel enable.
#define AES_KEY_STORE_READ_AREA_BUSY
Key store operation busy.
#define AES_AES_IV_2
AES initialization vector.
#define AES_AES_TAG_OUT_1
TAG.
#define AES_CTRL_INT_CLR_DMA_IN_DONE
Clear DMA in done interrupt.
#define AES_DMAC_CH0_EXTADDR
Channel 0 external address.
#define AES_CTRL_INT_EN_RESULT_AV
Result available interrupt enabled.
#define AES_KEY_STORE_READ_AREA
Key store read area.
uint8_t aes_auth_crypt_start(uint32_t ctrl, uint8_t key_area, const void *iv, const void *adata, uint16_t adata_len, const void *data_in, void *data_out, uint16_t data_len, struct process *process)
Starts an AES authentication/crypto operation.
#define AES_DMAC_CH1_EXTADDR
Channel 1 external address.
uint8_t aes_auth_crypt_get_result(void *iv, void *tag)
Gets the result of the AES authentication/crypto operation.
#define AES_AES_C_LENGTH_1
AES crypto length (MSW)
#define AES_AES_TAG_OUT_0
TAG.
#define AES_AES_TAG_OUT_3
TAG.
#define AES_CTRL_ALG_SEL_KEYSTORE
Select Key Store as DMA destination.
#define AES_AES_C_LENGTH_0
AES crypto length (LSW)
#define AES_CTRL_INT_STAT_DMA_IN_DONE
DMA data in done interrupt status.
#define AES_CTRL_INT_CLR_KEY_ST_WR_ERR
Clear key store write error status.
#define AES_KEY_STORE_SIZE_KEY_SIZE_192
Key size: 192 bits.
#define AES_CTRL_INT_CLR_RESULT_AV
Clear result available interrupt.
#define AES_DMAC_CH_DMALENGTH_DMALEN_S
Channel DMA length in bytes shift.
#define AES_CTRL_ALG_SEL
Algorithm select.
#define AES_CTRL_ALG_SEL_AES
Select AES engine as DMA source/destination.
#define AES_CTRL_INT_STAT
Interrupt status.
#define AES_DMAC_CH0_DMALENGTH
Channel 0 DMA length.
#define AES_CTRL_INT_EN
Interrupt enable.
#define AES_CTRL_INT_CLR_KEY_ST_RD_ERR
Clear key store read error status.
#define AES_KEY_STORE_WRITE_AREA
Key store write area.
#define AES_CTRL_INT_STAT_RESULT_AV
Result available interrupt status.
#define AES_AES_IV_1
AES initialization vector.
void crypto_register_process_notification(struct process *p)
Registers a process to be notified of the completion of a crypto operation.
static volatile uint64_t count
Num.
Header file for the ARM Nested Vectored Interrupt Controller.
Header file with register manipulation macro definitions.
Header file for the cc2538 ROM utility function library driver.